SHF: Small: Interconnection Networks: Topological Properties and Communication Algorithms

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Recent advances in technology have made the design of parallel computers with thousands of processors more feasible. Consequently, the study of different networks for linking processors is an integral part of the design of high-performance computers. This project will study the interconnection topologies of three important families of networks from the point of view of network efficiency. Examples of the type of problems to be considered include: algorithms for efficient communication among processors; effective placement of scarce or otherwise limited resources; and fault-tolerant communication algorithms in the presence of node/link failures. In addition to facilitating graduate training, the project would provide detailed insight for understanding various tradeoffs in designing interconnection networks for large multiprocessor architectures.