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SHF: Small: Architecture-Circuit Codesign of Ultra-Low Voltage On-Chip Caches

SHF: Small: Architecture-Circuit Codesign of Ultra-Low Voltage On-Chip Caches
SHF:小型:超低压片上高速缓存的架构电路协同设计
批准号:
1016262
负责人:
Nam Sung Kim
金额:
$42.98万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2010
资助国家:
美国
项目状态:
已结题
起止时间:
2010-09-01 至 2014-08-31

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中文摘要
翻译
功率效率已经成为高性能和低功耗处理器最关键的设计约束。为了使这类处理器的功耗最小化,电压缩放作为最强大的技术之一被广泛使用。然而,技术规模化增加了过程的可变性。这反过来又增加了片上存储器元件在低电压下的故障概率,并限制了处理器的电压缩放到最低工作电压。在这个项目中,将探索将电路和架构技术与信息理论相结合的协同解决方案,为未来的处理器提供可靠的超低电压片上缓存。该方法的新颖之处在于通过利用1)SRAM单元的尺寸和故障概率之间的强依赖性来设计成本和性能有效的片上缓存电路和架构;2)利用硬件和信息冗余修复缺陷细胞的现有方案和新方案的有效性;3)处理器存储系统在低工作电压和频率点下的特性。拟议的研究将对计算机体系结构、电路和信息理论社区产生具体而重要的影响,因为它需要分析有趣的和有代表性的工作负载;实现最先进的建筑、电路、信息理论技术;并发明了强大而有用的评估方法。由于大部分开发和研究工作将由研究生进行,工业界和学术界都将受益于受过良好教育和训练的雇员,以及当学生毕业并开始在其他地方就业时的直接技术转让。最后,这项研究的成功将对经济、教育和社会效益产生重大的社会影响,并对确保美国的领先地位发挥重要作用。
英文摘要
Power efficiency has become the most critical design constraint for both high-performance and low-power processors. To minimize power consumption of such processors, voltage scaling has been widely used as one of the most powerful techniques. However, technology scaling increases process variability. This, in turn, increases the failure probability of on-chip memory elements at low voltages and limits voltage scaling of processors to a minimum operating voltage. In this project, synergistic solutions combining circuit and architecture techniques with information theory will be explored to provide reliable, ultra-low voltage on-chip caches for future processors. The novelty of the proposed approaches lies in designing cost- and performance-effective on-chip cache circuits and architectures by exploiting 1) the strong dependence between size and failure probability of SRAM cells; 2) the effectiveness of existing and new schemes using the redundancy in hardware and information for repairing defective cells; and 3) the characteristics of processor memory systems at low operating voltage and frequency points. The proposed research will have a specific and significant impact on the computer architecture, circuit, and information theory communities since it requires analysis of interesting and representative workloads; realization of state-of-the-art architecture, circuit, information theory techniques; and invention of powerful and useful evaluation methodologies. Since most of the development and research work will be conducted by graduate students, both industry and academia will benefit from well-educated and trained employees, as well as direct technology transfer when students graduate and begin employment elsewhere. Finally, the success of this research will clearly have a major societal impact on economic, education and social benefits, and play an important role to assure the America's leading position.
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Collaborative Research: CCRI: Planning-C: Accelerated Infrastructure for Simulating Future Systems
CSR: Medium: Collaborative Research: Scale-Out Near-Data Acceleration of Machine Learning
CI-P: Planning Simulation Infrastructure Evaluation for Parallel/Distributed Computer Systems
  • 批准号:
    1512981
  • 项目类别:
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  • 资助金额:
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  • 财政年份:
    2015
  • 负责人:
    Nam Sung Kim
  • 依托单位:
CI-P: Planning Simulation Infrastructure Evaluation for Parallel/Distributed Computer Systems
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