SHF: Small: Architecture-Circuit Codesign of Ultra-Low Voltage On-Chip Caches

点击翻译按钮获取中文摘要

Power efficiency has become the most critical design constraint for both high-performance and low-power processors. To minimize power consumption of such processors, voltage scaling has been widely used as one of the most powerful techniques. However, technology scaling increases process variability. This, in turn, increases the failure probability of on-chip memory elements at low voltages and limits voltage scaling of processors to a minimum operating voltage. In this project, synergistic solutions combining circuit and architecture techniques with information theory will be explored to provide reliable, ultra-low voltage on-chip caches for future processors. The novelty of the proposed approaches lies in designing cost- and performance-effective on-chip cache circuits and architectures by exploiting 1) the strong dependence between size and failure probability of SRAM cells; 2) the effectiveness of existing and new schemes using the redundancy in hardware and information for repairing defective cells; and 3) the characteristics of processor memory systems at low operating voltage and frequency points. The proposed research will have a specific and significant impact on the computer architecture, circuit, and information theory communities since it requires analysis of interesting and representative workloads; realization of state-of-the-art architecture, circuit, information theory techniques; and invention of powerful and useful evaluation methodologies. Since most of the development and research work will be conducted by graduate students, both industry and academia will benefit from well-educated and trained employees, as well as direct technology transfer when students graduate and begin employment elsewhere. Finally, the success of this research will clearly have a major societal impact on economic, education and social benefits, and play an important role to assure the America's leading position.