CAREER: Overcoming the Many-Core Power Wall with Resistive Computation

随着晶体管数量随着摩尔？s定律，功耗已成为微处理器设计中的头号问题。传统的缩放理论依赖于与器件尺寸的减小成比例地减小电源电压，以保持动态功率处于受控状态。此外，泄漏功率也随着电源电压的降低而呈指数增加。这个项目提出了一种新的微架构设计技术，其目标是通过将现代微处理器的大部分功能迁移到自旋扭矩转移磁阻随机存取存储器（STT-MRAM）来避免功率墙。一种抗泄漏、非易失性、电阻式存储器技术。其核心思想是使用可扩展的抗泄漏STT-MRAM阵列和查找表来实现大部分片上存储和组合逻辑，以降低功耗，从而在固定功率预算下允许比传统实现方式更多的活动内核。为了实现这一目标，研究人员解决了从基本硬件构建块的电路级实现到更大规模微架构资源，控制策略和管理方法的开发的所有挑战。在电路层面，该项目探讨了基于STT-MRAM的内容可寻址存储器、寄存器、混合单元和查找表的设计。在体系结构层面，新的高速缓存体系结构，延迟隐藏技术，吞吐量优化和写功率缓解机制，采用整个存储器层次结构。新的混合存储器单元被探索，以消除写吞吐量和延迟问题，在大量写入队列和寄存器文件，而自适应写策略，循环流检测器，和微架构的资源分配机制限制写功率的一小部分是什么是可能的一个天真的实现。该项目还涉及基于查找表的功能单元和其他组合逻辑的设计，以及这些单元的设计和运行时重新配置。在处理器设计中利用STT-MRAM有可能在计算机系统的性能和可扩展性方面产生重大飞跃，对科学，技术和社会产生巨大的积极影响。该项目预计将为高效的功耗感知众核处理器铺平道路，这些处理器可以在固定的功耗范围内扩展到数百个活动核心。该项目的教育部分包括：（1）培训研究生和本科生的计算机体系结构，（2）引入一个新的存储系统课程，将电阻存储器集成到教学大纲中，以及（3）改进的计算机体系结构课程，包括本科生的设计经验。调查员计划参与当地的推广计划，促进妇女和代表性不足的少数民族参与计算机科学和工程，并发起一项新的努力，以增加少数民族在罗切斯特大学的计算机科学和电气和计算机工程课程的入学率。

As transistor count has increased exponentially with Moore?s Law, power has become the number one problem in microprocessor design. Traditional scaling theory relies on reducing supply voltages in proportion to the reduction in device dimensions to keep dynamic power in check. In addition, leakage power also increases exponentially with decreasing supply voltages. This project proposes a novel micro-architectural design technique whose goal is to avoid the power wall by migrating most of the functionality of a modern microprocessor to spin-torque transfer magneto-resistive random-access memory (STT-MRAM) ? a leakage resistant, non-volatile, resistive memory technology. The central idea is to implement most of the on-chip storage and combinational logic using scalable, leakage-resistant STT-MRAM arrays and lookup tables to lower power dissipation, thereby allowing many more active cores under a fixed power budget than a conventional implementation could afford. To accomplish this, the investigator addresses challenges all the way from the circuit-level implementation of fundamental hardware building blocks to the development of larger-scale micro-architectural resources, control policies, and management approaches. At the circuit level, the project explores the design of content-addressable memories, registers, hybrid cells, and lookup tables based on STT-MRAM. At the architecture level, novel cache architectures, latency-hiding techniques, throughput optimizations, and write-power mitigation mechanisms are employed throughout the memory hierarchy. Novel hybrid memory cells are explored to eliminate write throughput and latency problems in heavily written queues and register files, while adaptive write policies, loop stream detectors, and micro-architectural resource allocation mechanisms limit write power to a small fraction of what is possible under a naïve implementation. The project also addresses lookup-table based design of functional units and other combinational logic, as well as design- and run-time reconfiguration of these units.Leveraging STT-MRAM in processor design holds the potential to induce a significant leap in the performance and scalability of computer systems, with tremendous positive fallout to science, technology, and society at large. The project is expected to pave the way towards efficient power-aware many-core processors that can scale to hundreds of active cores under a fixed power envelope. The educational component of the project involves (1) training both graduate and undergraduate students in computer architecture, (2) the introduction of a a new memory systems course that integrates resistive memories into the syllabus, and (3) an improved computer architecture curriculum that includes design experience for undergraduates. The investigator plans involvement in local outreach programs promoting the participation of women and underrepresented minorities in computer science and engineering, and initiating a new effort to increase the enrollment of minorities in University of Rochester's computer science and electrical and computer engineering programs.