CRI: CI-P: Planning for an Innovative Dual-Path Computer Architecture Modeling Infrastructure for Highly Productive System Simulation and Emulation

CRI：CI-P：规划创新的双路径计算机架构建模基础设施，以实现高效的系统仿真和仿真

• 批准号: 1059202
• 负责人: Sangyeun Cho
• 金额: $ 10万
• 依托单位: University of Pittsburgh
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-02-01 至 2013-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1059202&HistoricalAwards=false
• 关键词: CRI; CI; Planning; Innovative; Dual

A detailed architecture simulator is indispensable for computer architects. Unfortunately, today's fastest simulators do not provide desirable simulation throughput. The problem becomes even more serious when the target of a study is next-generation systems having hundreds of processor cores. The lack of a fast and versatile multicore system simulator will seriously hamper the productivity of researchers, as well as their capability to produce timely technical innovations. Moreover, existing teaching infrastructures are predominantly for outdated single-core systems. This project is for planning the submission of a CI proposal to create and deploy a very fast and versatile simulation and emulation infrastructure that can model and evaluate a large multicore processor system using realistic workloads.The proposed infrastructure focuses on the core components of architectural research in the multicore paradigm - the design of the memory hierarchy and interconnect. The PIs plan to integate developed high-speed trace-based software and FPGA-based simulation and emulation techniques that provide orders of magnitude speedup over conventional simulation techniques. The proposed novel dual-path approach is based on a common graphical interface that allows a user to easily and quickly specify an architecture configuration and test it using these trace-driven simulation techniques.

一个详细的体系结构模拟器对于计算机架构师来说是必不可少的。不幸的是，今天最快的模拟器不提供理想的模拟吞吐量。当研究的目标是具有数百个处理器核心的下一代系统时，问题变得更加严重。缺乏快速和通用的多核系统模拟器将严重阻碍研究人员的生产力，以及他们及时进行技术创新的能力。此外，现有的教学基础设施主要用于过时的单核系统。该项目旨在规划提交CI提案，以创建和部署一个非常快速和通用的模拟和仿真基础设施，该基础设施可以使用真实的工作负载对大型多核处理器系统进行建模和评估。拟议的基础设施侧重于多核范式中架构研究的核心组件-存储器层次结构和互连的设计。PI计划整合开发的基于高速跟踪的软件和基于FPGA的仿真和模拟技术，这些技术提供了比传统仿真技术高几个数量级的加速。所提出的新颖的双路径方法是基于一个共同的图形界面，允许用户轻松，快速地指定一个架构配置和测试它使用这些跟踪驱动的仿真技术。