SHF: Medium: Compiler and Chip Multiprocessor Co-Design for Scalable Efficient Data Access and Communication

SHF：中：编译器和芯片多处理器协同设计，用于可扩展的高效数据访问和通信

• 批准号: 1064976
• 负责人: Alex Jones
• 金额: $ 60.17万
• 依托单位: University of Pittsburgh
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-03-15 至 2017-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1064976&HistoricalAwards=false
• 关键词: SHF; Medium; Compiler; Chip; Multiprocessor

Multi-core computing, where several processor cores are combined together into a single chip, has becomethe standard in computer processor design. In effect, each chip has become a small parallel computerand leveraging the processing power of parallel computing efficiently is a difficult challenge. Parallelcomputing attempts to accelerate computational tasks by separating the work into segments that can becalculated independently using different processors. Unfortunately, these processors need to communicatewith each other to complete the computational tasks correctly. This communication and the resultingaccess to data are major limiting factors to how much a computational task can be accelerated withmultiple processors.This research proposes a cooperatively designed system that considers the method for storing and accessingdata (memory), the method for communication between processors (network), the software thatcontrols how programs are executed (operating system), and the design of the program executables themselves(compilation) to maximize the program execution speed. The key observation is that while eachcomponent of the system can be improved independently, each component contains information that canhelp the other components to realize even greater benefits. Just as a transportation infrastructure requiresinformation about traffic patterns; for example, if traffic patterns were ignored and if highways connectrural areas and only side streets connect major cities, traffic would reach a standstill while highways areinefficiently used. Likewise, the communication network cannot be efficiently designed without informationfrom programs on communication patterns.The outcomes from this project will be the development of ?cross-layer? design concepts for multi-corecomputer architectures that will result in performance improvements and effective use of more processorcores within a single chip.

多核计算，将几个处理器核心组合成一个芯片，已经成为计算机处理器设计的标准。实际上，每个芯片已经成为一个小型的并行计算机，有效地利用并行计算的处理能力是一个艰巨的挑战。并行计算试图通过将工作分成可以使用不同处理器独立计算的部分来加速计算任务。不幸的是，这些处理器需要相互通信才能正确完成计算任务。这种通信和由此产生的对数据的访问是限制多处理器加速计算任务的主要因素。本研究提出了一个协同设计的系统，它考虑了存储和访问数据的方法（内存），处理器之间的通信方法（网络），控制程序如何执行的软件（操作系统），以及程序可执行程序本身的设计（编译），以最大限度地提高程序的执行速度。关键的观察是，虽然系统的每个组件都可以独立改进，但每个组件都包含可以帮助其他组件实现更大利益的信息。正如交通基础设施需要交通模式的信息一样；例如，如果交通模式被忽略，如果高速公路连接郊区，只有小巷连接主要城市，交通将陷入停滞，而高速公路的使用效率低下。同样，如果没有通信模式程序的信息，通信网络也不能有效地设计。这个项目的成果将是跨层的发展。多核计算机体系结构的设计概念，将导致性能改进和在单个芯片内有效地使用更多的处理器内核。