SHF: Medium: Compiler and Chip Multiprocessor Co-Design for Scalable Efficient Data Access and Communication

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Multi-core computing, where several processor cores are combined together into a single chip, has becomethe standard in computer processor design. In effect, each chip has become a small parallel computerand leveraging the processing power of parallel computing efficiently is a difficult challenge. Parallelcomputing attempts to accelerate computational tasks by separating the work into segments that can becalculated independently using different processors. Unfortunately, these processors need to communicatewith each other to complete the computational tasks correctly. This communication and the resultingaccess to data are major limiting factors to how much a computational task can be accelerated withmultiple processors.This research proposes a cooperatively designed system that considers the method for storing and accessingdata (memory), the method for communication between processors (network), the software thatcontrols how programs are executed (operating system), and the design of the program executables themselves(compilation) to maximize the program execution speed. The key observation is that while eachcomponent of the system can be improved independently, each component contains information that canhelp the other components to realize even greater benefits. Just as a transportation infrastructure requiresinformation about traffic patterns; for example, if traffic patterns were ignored and if highways connectrural areas and only side streets connect major cities, traffic would reach a standstill while highways areinefficiently used. Likewise, the communication network cannot be efficiently designed without informationfrom programs on communication patterns.The outcomes from this project will be the development of ?cross-layer? design concepts for multi-corecomputer architectures that will result in performance improvements and effective use of more processorcores within a single chip.