An Assessment of Options for Post-CMOS Emerging Research Devices and Related Materials: Four Workshops to be Held in 2012 in the Netherlands, Canada, France and San Francisco.

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ObjectiveThe objective of this project is to conduct an international series of four face-to-face workshopsto assess quantitatively the potential and status of four topics related to research on nanoelectronicsdevices and materials. The topics are: Emerging Research Memory Devices, Emerging ResearchLogic Devices, Emerging Research Architectures, and Emerging Research Materials critical forthe realization of specific nanoelectronics devices. Participants and contributors to theseworkshops will include academic and industrial domain experts. The outputs of these workshopswill guide and input preparation of the 2013 International Technology Roadmap for Semiconductorschapters on Emerging Research Devices and Emerging Research Materials. This grant willbe used to pay partial travel expenses for some presenters, particularly academics, requestingtravel assistance.The workshops series will focus on the relationship between the Semiconductor Industry asit endeavors to continue to advance semiconductor technology and the work of the NationalNanotechnology Initiative (NNI) research community. One purpose of these meetings is to evaluatethe potential and status of each specific nanotechnology entry identified by the ITRS ERD/ERMWorking Groups as having potential to enable a new paradigm for information processing. Anotherpurpose is to identify research opportunities that, if addressed, will benefit the SemiconductorIndustry and fall within the scope of the NNI research agenda. Presenters will be providedwith a list of questions that are intended to stimulate discussions during the workshops.Each workshop will be documented by a report described below.Intellectual MeritIn bringing together leading academic and industrial scientists to discuss, debate and reachconsensus on the potential performance and key scientific challenges related to several emergingresearch memory and logic device technologies, these workshops will provide an excellent forumfor intellectual pursuit and discernment of important/limiting scientific issues related toapproaches to information processing. The intellectual merit of these workshops is illustratedby way of example.In the first example, the physics of operation and extreme scaling projections are not wellunderstood for ?select devices? required for use in nanoscale memory arrays. These selectdevices are needed to employ a new class of non-volatile memory cells, called resistive randomaccess memory (ReRAM),that may replace NAND flash for technology generations beyond the 16nmtechnology node. Generally speaking, a memory cell in an array can be viewed as being composedof two fundamental components: a ?storage node?, which is usually characterized by the physicsof operation of the particular memory device used, and a ?selector?. The selector is a devicewhich allows a given memory cell in an array to be singularly addressed for read or writeoperation without addressing its nearest neighbor cells. It is a non-linear element, whichcan operate as a switch, such as a diode-type, or as a resistive-switch-type structure. Thelatter category includes novel concepts such as Mott switches, threshold switches, and mixedionic electronic conduction switches. Understanding the dominant physics related to theirnon-linear I-V characteristics is essential to employing these select devices in a highlydense non-volatile ReRAM crossbar architecture. It should be noted that for several advancedconcepts of ReRAM, the storage node in principle can be scaled down below 10 nm, and the memorydensity will be limited by a somewhat larger conventional three-terminal select device. Thusthe select device represents a serious bottleneck for scaling a ReRAM memory cell to 16 nmand beyond. Application of these new non-volatile memory devices to a crossbar memory structurewill enable a paradigm shift to a new storage class memory (SCM) off-chip memory architecturediscussed below.Another example, related to logic, is a family of new nanoelectronic low subthreshold-swingdevices: e.g., negative Cg devices. These devices offer the attractive possibility of performinghigh speed logic while dissipating much lower power compared to a conventional MOSFET. Thecircuit design and the academic research communities have a expressed a strong interest forthe ERD Technical Working Group to explore the physics of operation of these devices and thecircuit design space in which they can operate in order to better understand their potentialperformance. This information will provide important input to these communities regardingtheir accelerating development of low-power electronics.Broader ImpactBy carefully assessing the potential performance and scientific/technological challenges foreach new memory select device and of new low-power logic devices, as well as emerging architectures,these workshops will provide important documented inputs to the research community as theypursue their exploration of many emerging research devices.One venue being initiated to obtain broad dissemination of this information is the editingand publication of a comprehensive book on nanoelectronics entitled ?Emerging NanoelectronicDevices?. A proposal is under review by a major publisher who has expressed considerable interest.Furthermore, the educational value and planning impact of these workshops on the internationalresearch community are quite substantial. Several universities (e.g., Stanford, U. Minnesota,U. Tokyo,?) use the ITRS chapters on Emerging Research Devices and Emerging Research Materialsresulting from these workshops as texts in their Nanoelectronics courses. Also several internationalresearch funding agencies (e.g., SRC, NSF, and NIST Nanoelectronics Research Initiative, theEU Framework Program 8, ?) use the material in these chapters as inputs to their decisionson research directions in their Nanoelectronics research programs.