Design of Reliable High-Speed Links with Unreliable Circuits

具有不可靠电路的可靠高速链路的设计

基本信息

项目摘要

The objective of this research is to create a new failure-resistant architecture for high-speed digital links to enable the next generation of high-performance communication and computing systems. The failure-resistant architecture is based on maximum a posteriori (MAP) detection and overcomes not only challenging channel impairments, but also deterministic impairments incurred in the interface and timing circuitry. The system-level protection given by MAP detection offers new opportunities in the design of power-efficient analog-to-digital converters (ADCs) and timing generation based on seas of digital gates that exploit the variations and errors in unreliable, deeply scaled devices. The MAP detector itself is enhanced using an iterative, soft message-passing algorithm to unleash its full throughput potential while providing tolerance against underlying circuit failures. The new link techniques developed in this research will improve both the computing capability and the energy efficiency of large data centers needed for cloud computing. The techniques also impact personal and mobile computing by delivering more efficient serial links such as the next-generation universal serial bus (USB). The interdisciplinary nature of this project encourages a tight integration of mixed-signal circuits, digital circuits and signal processing research and provides excellent training to students through research and industry internships.
本研究的目标是为高速数字链路创建一种新的抗故障架构,以实现下一代高性能通信和计算系统。该抗故障架构基于最大后验概率(MAP)检测,不仅克服了具有挑战性的信道损伤,而且还克服了接口和定时电路中发生的确定性损伤。MAP检测提供的系统级保护为设计高能效模数转换器(ADC)和基于海量数字门的时序生成提供了新的机会,这些数字门利用了不可靠的深度扩展器件中的变化和错误。MAP检测器本身使用迭代的软消息传递算法来增强,以释放其全部吞吐量潜力,同时提供对底层电路故障的容忍度。本研究开发的新链路技术将提高云计算所需的大型数据中心的计算能力和能源效率。这些技术还通过提供更高效的串行链路(如下一代通用串行总线(USB))来影响个人和移动的计算。该项目的跨学科性质鼓励混合信号电路,数字电路和信号处理研究的紧密结合,并通过研究和行业实习为学生提供优秀的培训。

项目成果

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Zhengya Zhang其他文献

Hardware acceleration of iterative image reconstruction for X-ray computed tomography
X 射线计算机断层扫描迭代图像重建的硬件加速
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine
基于 ReRAM 的 8 位 20.7 TOPS/W 多层单元计算引擎
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks
支持条件神经网络动态执行的 0.23mW 异构深度学习处理器
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation
3.7 个 1920×1080 30fps 2.3TOPS/W 立体深度处理器,用于强大的自主导航
  • DOI:
    10.1109/isscc.2017.7870261
  • 发表时间:
    2017
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Ziyun Li;Qing Dong;Mehdi Saligane;B. Kempke;Shijia Yang;Zhengya Zhang;R. Dreslinski;D. Sylvester;D. Blaauw;Hun
  • 通讯作者:
    Hun
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS
用于 28nm CMOS 微型自主车辆导航的 470mV 2.7mW 特征提取加速器

Zhengya Zhang的其他文献

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{{ truncateString('Zhengya Zhang', 18)}}的其他基金

SHF: Small: Native Stochastic Computing Based on Memristors
SHF:小型:基于忆阻器的本机随机计算
  • 批准号:
    1217972
  • 财政年份:
    2012
  • 资助金额:
    $ 21.6万
  • 项目类别:
    Standard Grant
CAREER: Removing Energy Barrier Towards Capacity-Approaching Information Transmission and Storage
职业:消除能量障碍,实现接近容量的信息传输和存储
  • 批准号:
    1054270
  • 财政年份:
    2011
  • 资助金额:
    $ 21.6万
  • 项目类别:
    Continuing Grant

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