Collaborative Research: Localized, Layered Formal Hardware/Software Resilience Methods

对提高性能和功能的追求已经将计算机芯片推向了其功率/能量和可靠性的物理极限。未来的计算系统可能会遭受高故障率的困扰，从而破坏它们的可编程性和可用性。该研究项目将利用现有技术并发明新技术来检测、隔离和从故障中恢复，并确保整个系统的弹性，对性能的影响最小。该项目利用了过去关于形式化方法的丰富工作，这些方法在发现系统中的逻辑错误方面取得了成功。新开发的正式方法将侧重于增强弹性。该项目还将探索性能、功率和弹性之间的内在权衡。该项目将开发一个可扩展的平台，用于弹性方法的实证评估。该平台将由可编程芯片和配套的软件组件组成。该项目将促进考虑可靠性的新系统设计方法的发展。通过开发和发布评估方法的工具，它将有助于填补并行系统领域中易于使用的弹性研究基础设施的严重空白。该项目还将开发和发布严格指定的弹性感知系统接口。该项目强调学生培训，包括招生和引入与弹性研究相结合的新课程。

The drive for increased performance and functionality has pushed computer chips to their physical limits of power/energy and reliability. Future computing systems are likely to suffer from high fault rates, undermining their programmability and usability. This research project will leverage existing techniques and invent new techniques to detect, isolate, and recover from faults and to ensure overall system resilience, with minimal impact on performance. The project taps into the rich body of past work on formal methods, which have been successful in finding logical errors in systems. Newly developed formal methods will focus on resilience enhancement. The project will also explore the inherent trade-offs between performance, power, and resilience. The project will develop an extensible platform for empirical evaluation of resilience methods. This platform will be comprised of programmable chips and accompanying software components.This project will foster the development of new system design methods which take reliability into account. It will help fill a serious void in readily usable infrastructures for resiliency studies in the realm of parallel systems by developing and releasing tools for evaluating the methods. The project will also develop and release rigorously specified resilience-aware system interfaces. The project emphasizes student training, including student recruitment and introduction of new classes that are integrated with resilience research.