Compiler-driven Design Space Exploration for Multiple FPGA Systems

该项目致力于通过程序分析、并行化编译器技术和行为综合工具的协同协作，将使用命令式编程语言(如C)编写的应用程序映射到多个FPGA计算系统。拟议的研究涉及基于高级程序分析的计算核心之间的任务执行的系统级分区和调度，以及管理内部和外部存储器之间以及任务之间的数据存储和移动。该项目是第一个将并行化编译器技术与EDA综合技术进行全面、自动集成的项目。这也是第一次尝试在编译器中集成高级循环变换，这些变换由商业上可用的合成工具提供的估计指导。最终结果是一种现实而准确的设计空间探索策略，我们相信该策略广泛适用于当前和未来的多个FPGA系统以及未来的片上系统(SoC)。这项研究中提出的解决系统级问题的自动化应用程序映射方法最终将允许设计人员探索更广泛的SoC系统应用程序映射策略。

This project focuses on system-level mapping of applications written in imperative programming languages such as C to multiple FPGA computing systems by the synergistic collaboration of program analysis, parallelizing compiler technology and behavioral synthesis tools. The proposed research addresses system-level partitioning and scheduling of the execution of tasks among computing cores based on high-level program analysis as well as managing the storage and movement of data between both internal and external memories and between tasks. This project is the first comprehensive, and automatic, integration of parallelizing compiler technology with EDA synthesis. It is also the first attempt to integrate in a compiler high-level loop transformations guided by estimates provided by commercially available synthesis tools. The end result is a realistic and accurate design space exploration strategy we believe is widely applicable to current and future multiple FPGA systems as well as future System-On-a-Chip (SoC) systems. An automated application mapping approach that addresses system-level issues as proposed in this research will ultimately allow designers to explore a wider range of application mapping strategies for SoC systems.