Compiler-driven Design Space Exploration for Multiple FPGA Systems

该项目的重点是通过程序分析，并行编译器技术和行为合成工具的协同合作，将以命令式编程语言（如C）编写的应用程序映射到多个FPGA计算系统。所提出的研究解决了基于高级程序分析的计算核心之间的任务执行的系统级分区和调度，以及管理内部和外部存储器之间以及任务之间的数据的存储和移动。这个项目是第一个全面的，自动的，集成的并行编译技术与EDA综合。这也是第一次尝试集成在一个编译器的高层次循环转换的指导下提供的估计商业合成工具。最终的结果是一个现实和准确的设计空间探索策略，我们相信这是广泛适用于当前和未来的多个FPGA系统以及未来的片上系统（SoC）系统。一个自动化的应用程序映射方法，解决系统级的问题，在这项研究中提出的，最终将允许设计人员探索更广泛的SoC系统的应用程序映射策略。

This project focuses on system-level mapping of applications written in imperative programming languages such as C to multiple FPGA computing systems by the synergistic collaboration of program analysis, parallelizing compiler technology and behavioral synthesis tools. The proposed research addresses system-level partitioning and scheduling of the execution of tasks among computing cores based on high-level program analysis as well as managing the storage and movement of data between both internal and external memories and between tasks. This project is the first comprehensive, and automatic, integration of parallelizing compiler technology with EDA synthesis. It is also the first attempt to integrate in a compiler high-level loop transformations guided by estimates provided by commercially available synthesis tools. The end result is a realistic and accurate design space exploration strategy we believe is widely applicable to current and future multiple FPGA systems as well as future System-On-a-Chip (SoC) systems. An automated application mapping approach that addresses system-level issues as proposed in this research will ultimately allow designers to explore a wider range of application mapping strategies for SoC systems.