SHF: Small: Architecting Stacked DRAM as Gigascale Cache, or Fast Memory, or Both

SHF：小型：将堆叠 DRAM 架构为千兆级高速缓存或快速内存，或两者兼而有之

• 批准号: 1319587
• 负责人: Moinuddin Qureshi
• 金额: $ 45万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-09-01 至 2017-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1319587&HistoricalAwards=false
• 关键词: SHF; Small; Architecting; Stacked; DRAM

As the computing industry steps into the many-core regime, the main memory system hasbecome one of the key bottlenecks that limits both performance and scalability. To address thesechallenges, the memory industry is developing 3D-stacked DRAM technology. Die stacking canprovide lower latency, much higher bandwidth, and significantly reduced energy dissipation.Unfortunately, stacked memory is unlikely to have sufficient capacity to completely replacetraditional DRAM. Therefore, future memory systems will likely use stacked memory incombination with off-chip DRAM, either architecting stacked DRAM as a giga-scale cache or asheterogeneous main memory. However, to fully utilize the potential of stacked memory, thesystem architecture must make choices that exploit the unique latency and bandwidthcharacteristics offered by stacked DRAM. For example, simply applying traditional "well-understood"cache designs and memory designs to stacked DRAM results in low performanceand poor bandwidth utilization.This project first looks at caching organizations and management strategies for stacked DRAMthat are tailored to exploit latency and bandwidth properties of 3D stacking. It then looks atmemory organizations that can incorporate stacked memory as part of memory address space,without relying on OS support to exploit temporal locality and still perform memorymanagement at fine granularity. Finally, this project investigates morphable architectures that candynamically reconfigure the stacked DRAM between cache structure and main memory, in orderto conserve power and optimize performance depending on the workload requirements. Theresearch solutions in this study will thus help future systems obtain an order of magnitudeimprovement in both bandwidth and energy-efficiency from the effective use of memorystacking.

随着计算行业逐步进入众核体系，主存系统已经成为限制性能和可扩展性的关键瓶颈之一。为了应对这些挑战，存储器行业正在开发3D堆叠DRAM技术。芯片堆叠可以提供更低的延迟、更高的带宽和显著降低的能耗。不幸的是，堆叠存储器不太可能有足够的容量完全取代传统的DRAM。因此，未来的内存系统将可能使用堆叠内存结合片外DRAM，无论是架构堆叠DRAM作为一个千兆规模的高速缓存或作为异构主存储器。然而，为了充分利用堆栈存储器的潜力，存储器架构必须做出选择，利用堆栈DRAM提供的独特延迟和带宽特性。例如，简单地将传统的“众所周知”的高速缓存设计和内存设计应用于堆叠DRAM会导致低性能和低带宽利用率。本项目首先着眼于堆叠DRAM的高速缓存组织和管理策略，这些组织和管理策略是针对利用3D堆叠的延迟和带宽特性而定制的。然后，它着眼于内存组织，可以将堆栈内存作为内存地址空间的一部分，而不依赖于操作系统的支持，以利用时间局部性，仍然执行内存管理在细粒度。最后，本项目研究了可变形的体系结构，可以动态地重新配置缓存结构和主存储器之间的堆栈DRAM，以节省功率和优化性能取决于工作负载的要求。因此，本研究中的研究解决方案将有助于未来的系统从有效使用存储器堆叠中获得带宽和能源效率的数量级改进。