SHF: Small: Architecting Stacked DRAM as Gigascale Cache, or Fast Memory, or Both

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As the computing industry steps into the many-core regime, the main memory system hasbecome one of the key bottlenecks that limits both performance and scalability. To address thesechallenges, the memory industry is developing 3D-stacked DRAM technology. Die stacking canprovide lower latency, much higher bandwidth, and significantly reduced energy dissipation.Unfortunately, stacked memory is unlikely to have sufficient capacity to completely replacetraditional DRAM. Therefore, future memory systems will likely use stacked memory incombination with off-chip DRAM, either architecting stacked DRAM as a giga-scale cache or asheterogeneous main memory. However, to fully utilize the potential of stacked memory, thesystem architecture must make choices that exploit the unique latency and bandwidthcharacteristics offered by stacked DRAM. For example, simply applying traditional "well-understood"cache designs and memory designs to stacked DRAM results in low performanceand poor bandwidth utilization.This project first looks at caching organizations and management strategies for stacked DRAMthat are tailored to exploit latency and bandwidth properties of 3D stacking. It then looks atmemory organizations that can incorporate stacked memory as part of memory address space,without relying on OS support to exploit temporal locality and still perform memorymanagement at fine granularity. Finally, this project investigates morphable architectures that candynamically reconfigure the stacked DRAM between cache structure and main memory, in orderto conserve power and optimize performance depending on the workload requirements. Theresearch solutions in this study will thus help future systems obtain an order of magnitudeimprovement in both bandwidth and energy-efficiency from the effective use of memorystacking.