SHF: Small: Architecting Stacked DRAM as Gigascale Cache, or Fast Memory, or Both

随着计算行业步入多核时代，主存系统已经成为限制性能和可伸缩性的关键瓶颈之一。为了应对这些挑战，存储器行业正在开发3d堆叠DRAM技术。芯片堆叠可以提供更低的延迟，更高的带宽，并显着降低能量消耗。不幸的是，堆叠内存不太可能有足够的容量来完全取代传统的DRAM。因此，未来的存储系统可能会将堆叠内存与片外DRAM结合使用，要么将堆叠DRAM架构为千兆级缓存，要么作为异构主存储器。然而，为了充分利用堆叠内存的潜力，系统架构必须做出选择，利用堆叠DRAM提供的独特延迟和带宽特性。例如，简单地将传统的“众所周知的”缓存设计和内存设计应用于堆叠DRAM会导致低性能和低带宽利用率。该项目首先着眼于为利用3D堆叠的延迟和带宽特性而量身定制的堆叠dram的缓存组织和管理策略。然后，它着眼于可以将堆叠内存作为内存地址空间的一部分的内存组织，而不依赖于操作系统支持来利用时间局部性，并且仍然以细粒度执行内存管理。最后，本项目研究了可变架构，可以动态地重新配置缓存结构和主存之间的堆叠DRAM，以便根据工作负载要求节省电力和优化性能。因此，本研究中的研究解决方案将有助于未来系统从有效使用内存堆栈中获得带宽和能源效率的数量级改进。

As the computing industry steps into the many-core regime, the main memory system hasbecome one of the key bottlenecks that limits both performance and scalability. To address thesechallenges, the memory industry is developing 3D-stacked DRAM technology. Die stacking canprovide lower latency, much higher bandwidth, and significantly reduced energy dissipation.Unfortunately, stacked memory is unlikely to have sufficient capacity to completely replacetraditional DRAM. Therefore, future memory systems will likely use stacked memory incombination with off-chip DRAM, either architecting stacked DRAM as a giga-scale cache or asheterogeneous main memory. However, to fully utilize the potential of stacked memory, thesystem architecture must make choices that exploit the unique latency and bandwidthcharacteristics offered by stacked DRAM. For example, simply applying traditional "well-understood"cache designs and memory designs to stacked DRAM results in low performanceand poor bandwidth utilization.This project first looks at caching organizations and management strategies for stacked DRAMthat are tailored to exploit latency and bandwidth properties of 3D stacking. It then looks atmemory organizations that can incorporate stacked memory as part of memory address space,without relying on OS support to exploit temporal locality and still perform memorymanagement at fine granularity. Finally, this project investigates morphable architectures that candynamically reconfigure the stacked DRAM between cache structure and main memory, in orderto conserve power and optimize performance depending on the workload requirements. Theresearch solutions in this study will thus help future systems obtain an order of magnitudeimprovement in both bandwidth and energy-efficiency from the effective use of memorystacking.