BSF:2012171:Progress Guarantees for Hardware Transactional Memory
BSF:2012171:Progress Guarantees for Hardware Transactional Memory
批准号:
1331141
负责人:
Maurice Herlihy
金额:
$4.5万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2013
资助国家:
美国
项目状态:
已结题
起止时间:
2013-10-01 至 2018-09-30
中文摘要
该项目是美国-以色列计算机科学合作(USICCS)计划的一部分。通过该计划,NSF和美国-以色列两国科学基金会(BSF)共同支持美国研究人员和以色列研究人员之间的合作。直到最近,处理器的速度每年都在提高,因为晶体管和导线等基本电路元件变得更小,速度更快。 2005年左右,情况发生了变化。每年,电路元件继续变得更小,但它们不再变得更快,因为它们过热。 作为回应,处理器制造商现在在每个芯片上放置多个处理器。 这些多核架构不是以更快的速度执行一个任务,而是并行执行多个任务。计算机体系结构的这场革命给软件设计者带来了巨大的挑战,他们现在必须构建软件以利用不断增加的并行性,而不是速度。最近,英特尔和IBM宣布了新的多核体系结构,直接支持事务的硬件,这是一种编程抽象,有望使并行软件更容易设计。 向硬件事务的转变可以给我们编程多核机器的方式带来根本性的积极变化,现在是时候了解这种转变的影响了。 拟议的研究将围绕重新思考和重新设计基本的同步结构,如锁,内存管理,以及一系列并发数据结构,如堆,哈希表和跳跃列表,以及这些数据结构的进度保证如何与内存管理等问题相互作用。
英文摘要
This project is funded as part of the United States-Israel Collaboration in Computer Science (USICCS) program. Through this program, NSF and the United States - Israel Binational Science Foundation (BSF) jointly support collaborations among US-based researchers and Israel-based researchers. Until recently, processors became faster every year, because basic circuit elements like transistors and wires became both smaller and faster. Around 2005, things changed. Every year, circuits elements continue to become smaller, but they no longer become faster, because they overheat. In response, processor manufacturers now put multiple processors on each chip. Instead of doing one task faster, these multicore architectures do many tasks in parallel. This revolution in computer architecture presents enormous challenges to software designers, who must now structure software to exploit increasing parallelism, not speed.Recently, Intel and IBM announced new multicore architectures with direct hardware support for transactions, a programming abstraction that promises to make parallel software much easier to design. The move to hardware transactions can bring about a fundamental positive change in the way we program multicore machines, and now is the time to understand the implications of such a shift. The proposed research will center around rethinking and redesigning basic synchronization structures such as locks, memory management, and a range of concurrent data structures such as heaps, hash tables, and skip lists, and on how progress guarantees for these data structures interact with issues such as memory management.
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