BSF:2012171:Progress Guarantees for Hardware Transactional Memory

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This project is funded as part of the United States-Israel Collaboration in Computer Science (USICCS) program. Through this program, NSF and the United States - Israel Binational Science Foundation (BSF) jointly support collaborations among US-based researchers and Israel-based researchers. Until recently, processors became faster every year, because basic circuit elements like transistors and wires became both smaller and faster. Around 2005, things changed. Every year, circuits elements continue to become smaller, but they no longer become faster, because they overheat. In response, processor manufacturers now put multiple processors on each chip. Instead of doing one task faster, these multicore architectures do many tasks in parallel. This revolution in computer architecture presents enormous challenges to software designers, who must now structure software to exploit increasing parallelism, not speed.Recently, Intel and IBM announced new multicore architectures with direct hardware support for transactions, a programming abstraction that promises to make parallel software much easier to design. The move to hardware transactions can bring about a fundamental positive change in the way we program multicore machines, and now is the time to understand the implications of such a shift. The proposed research will center around rethinking and redesigning basic synchronization structures such as locks, memory management, and a range of concurrent data structures such as heaps, hash tables, and skip lists, and on how progress guarantees for these data structures interact with issues such as memory management.