Collaborative Research:XPS:CLCCA: Cross-layer Thermal Reliability Management in 3D Integrated Heterogeneous Processor for Breaking the Power and Bandwidth Walls

通过 TSV（硅通孔）垂直互连的 CPU、GPU 和 DRAM 芯片的 3D 堆叠集成正在成为未来并行和可扩展计算系统的关键支持技术。这种 3D 异构处理器 (3DHP) 预计将提供更高的带宽、更低的延迟和功耗，以打破功率和带宽壁垒。尽管有如此显着的优势，3DHP 也带来了从未被充分探索和解决的新的特定领域挑战。显着更高的功率密度、更薄的基板和层间介电材料的低导热率都使得热管理成为威胁3DHP整体可靠性和性能的严重问题。该项目旨在通过整体跨层方法解决 3DHP 的热完整性问题。各个目标系统层（包括物理层、架构层和运行时层）的三个主要热完整性问题及其相关性将由具有必要背景和专业知识的三名 PI 组成的团队进行广泛调查。所提出的新颖跨层方法包括：1）物理层的自校准片上温度/应力协同传感器框架，2）架构层的自适应错误检测和纠正（EDAC）和DRAM刷新引擎，用于在CPU、GPU和DRAM芯片之间可靠地存储和传输数据，以及3）动态热可靠性管理（DTRM）框架，用于在运行时层对工作负载和硬件资源之间的交互进行细粒度控制。所提出的分层技术将紧密交织，以产生最协同的结果。该项目的研究将为可行的基于 3DHP 的并行和可扩展计算系统提供可靠的热完整性设计和仿真框架。

3D stacked integration of CPU, GPU and DRAM dies vertically interconnected by TSVs (Through-Silicon Vias) is emerging as a key enabling technology for parallel and scalable computing systems of tomorrow. Such 3D Heterogeneous Processor (3DHP) is expected to deliver much higher bandwidth, lower latency and power consumption to break the power and bandwidth walls. Despite such significant benefits, 3DHP comes with new domain-specific challenges that have never been fully explored and addressed. Significantly higher power density, thinned substrate and low thermal conductivity of inter-layer dielectric material all make thermal management a serious problem that threatens overall reliability and performance of 3DHP. This project aims to address this thermal-integrity issue of 3DHP through a holistic cross-layer approach. Three major thermal integrity issues at respective target system layers including physical, architecture and runtime layers and their correlations will be extensively investigated by a team of three PIs with necessary background and expertise. The proposed novel cross-layer approach includes: 1) Self-calibrated on-chip temperature/stress co-sensor framework at physical layer, 2) Adaptive Error Detection & Correction (EDAC) and DRAM refresh engine at architecture layer for reliable storage and transfer of data among CPU, GPU and DRAM dies, and 3) Dynamic Thermal Reliability Management (DTRM) framework for fine-grained control of interaction between workloads and HW resources at runtime layer. The proposed layered techniques will be tightly interwoven to bring out the most synergistic results. The research in this project will result in a solid thermal-integrity design and simulation framework for viable 3DHP-based parallel and scalable computing systems.