SHF: Small: Toward True Heterogeneous Computing: Concurrent Data Structure Design and Optimization

用于处理现代计算机中密集计算任务的图形处理单元（GPU）的引入改变了并行计算的格局。这种现象的核心是大规模多线程、数据并行的计算机体系结构，具有令人印象深刻的加速等级，提供低成本的超级计算以及具有吸引力的功耗预算。虽然GPU可以处理计算密集型任务，但计算机的大脑，中央处理器（CPU），擅长处理面向延迟的任务。CPU和GPU之间通过共享数据结构进行通信，为了避免在处理不同级别CPU和GPU的异构应用程序时CPU和GPU的使用不匹配，需要有效地设计共享数据结构。该项目旨在通过设计和实现高度可伸缩的并发数据结构（cds），确保无论工作负载如何，始终存在这种效率。开发的cds通过开发库和真实的异构工作负载进行实际测试。项目的结果、发现和成果将贡献给开源社区，并通过学术出版物、在线材料和网站向社区传播。最近在GPU驱动的计算平台上对细粒度数据共享和线程通信的支持允许应用程序通过共享虚拟内存中的数据结构从简单、廉价、多样化的CPU和GPU协作模型中受益。在新启用的CPU-GPU协作模型中，面向延迟的CPU线程和面向吞吐量的GPU线程通过共享数据结构相互同步和通信。因此，这些数据结构的效率对于真正的异构计算的成功至关重要。众所周知，设计一个能够跨不同并发级别很好地伸缩的CDS是一项非常具有挑战性的任务。异构平台上增加的并发性使其在性能和正确性方面更具挑战性。虽然在传统cpu上下文中已经进行了大量的研究，但在异构平台上下文中所知甚少。当与硬件协同设计时，可以实现高度可扩展的CDS设计的全部潜力；当前的硬件是第一代设计，没有很好地理解处理器间细粒度数据共享和线程通信。虽然该项目的主要目标是设计高效的cds，其性能可以在异构平台上的并发性需求范围内很好地扩展，但另一个重要目标是改进和优化对高效细粒度数据共享线程通信至关重要的硬件支持，例如处理器间缓存一致性、GPU线程调度和SIMD感知优化。为此，本研究采用软硬件协同设计方法，采用六个具体研究目标（减少负载、开发争用管理方案、优化CPU-GPU缓存一致性协议、SIMD感知优化、架构感知操作映射、库和实际应用程序开发）来解决三个基本挑战（顺序瓶颈、内存争用和架构异构）。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The introduction of Graphics Processing Units (GPU) for handling intensive computing tasks in modern-day computers has changed the landscape for parallel computing. At the core of this phenomenon are massively-multithreaded, data-parallel computer architectures with impressive acceleration ratings, offering low-cost supercomputing together with attractive power budgets. While the GPU can handle computation-intensive tasks providing high through, the computer's brains, the Central Processing Unit (CPU), is good at handling latency-oriented tasks. The CPU and GPU communicate with each other through shared data structures that need to be efficiently designed in order to avoid mismatch in the use of the CPU and GPU when handling heterogeneous applications that tax the CPU and GPU at different levels. This project seeks to ensure such efficiencies always exist regardless of workload, through the design and implementation of highly-scalable Concurrent Data Structures (CDSs). The developed CDSs are practically tested by developing library and real-world true heterogeneous workloads. The results, findings, and outcomes of the project are contributed to open-source community and disseminated through scholarly publications, online materials, and websites to the community.The recent support of fine-grained data sharing and thread communication on GPU-powered computing platforms allows applications to benefit from easy, cheap, diverse CPU and GPU collaboration models through data structures in shared virtual memory. In newly enabled CPU-GPU collaboration models, latency-oriented CPU threads and throughput-oriented GPU threads synchronize and communicate with one another through shared data structures. Therefore, the efficiency of these data structures is crucial for the success of true heterogeneous computing. Designing a CDS that scales well across different concurrency levels is known to be a very challenging task. The increased concurrency on heterogeneous platforms makes it even more challenging with respect to performance and correctness. While a significant amount of research has been done in the context of traditional CPUs, there is very little known in the context of heterogeneous platforms. The full potential of a highly-scalable CDS design can be achieved when co-designed with hardware; current hardware is the first generation designs that have not benefited from a good understanding of inter-processor fine-grained data sharing and thread communication. While the primary objective of the project is designing efficient CDSs whose performance scales well across a spectrum of concurrency demands on heterogeneous platforms, the other important target is to improve and optimize hardware support crucial for efficient fine-grained data sharing thread communication, such as inter-processor cache coherence, GPU thread scheduling, and SIMD aware optimizations. To that end, this research takes software-hardware co-design approach using six specific research aims (reducing loads, developing contention management schemes, optimizing CPU-GPU cache coherence protocol, SIMD aware optimization, architecture aware operation mapping, library and real-world application development) to address three fundamental challenges (sequential bottlenecks, memory contention, and architectural heterogeneity).This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.