Collaborative Research: Computational Study of Low Volume Solder Interconnects for 3D Integrated Circuit Packaging

合作研究：3D 集成电路封装小体积焊料互连的计算研究

• 批准号: 1462204
• 负责人: Yongmei Jin
• 金额: $ 15万
• 依托单位: Michigan Technological University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-04-01 至 2019-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1462204&HistoricalAwards=false
• 关键词: Collaborative; Research; Computational; Study; Low

Moore's Law, which predicts that the number of transistors in an integrated circuit doubles approximately every two years, has been a major driver for the US economy for decades. Unfortunately, technological and fundamental challenges associated with continued device shrinking make the current rate of progress unsustainable. Recently, 3D integrated circuit technology has emerged as a leading approach to keep up with Moore's Law by stacking chips rather than by shrinking device dimensions. To achieve 3D integration, new joining technologies for interconnection and stacked bonding must be developed. Bonding by low volume solder interconnects is specially promising due to their good electrical, thermal, and mechanical properties. This collaborative research award supports fundamental research to obtain the knowledge needed for the development of low volume solder interconnects. Research results will not only help realize the full potential of this new bonding technique in 3D integrated circuit packaging, but also be used to improve joining methodologies important in the aerospace and nuclear power industries and in power electronics and thermal management applications. Moreover, the project will help establish an effective collaboration between the two PIs who are both from underrepresented groups.The small dimensions of low volume solder interconnects make it possible for the solder joints to solidify isothermally through the formation of intermetallic compounds at the expense of the liquid solders. This technique, also known as Transient Liquid Phase Bonding, allows the formation of a joint at temperatures lower than the expected operating conditions, minimizing damage to the temperature-sensitive components of the circuits from overheating. However, the small dimensions of low volume solder interconnects lead to large current densities during operation. These large current densities induce large electrical, thermal, and mechanical driving forces which give rise to complex microstructural processes. This research aims to advance the fundamental understanding of the complex microstructure processes in low volume solder interconnects, in particular about the important microscopic mechanisms governing processing-microstructure-property-performance relationships. The research team will develop an integrated multi-physics phase field modeling and perform systematic simulation studies of the microstructure formation and evolution during processing, operation, and damage of low volume solder interconnects. The simulations will be used to correlate macroscopic processing parameters and operating conditions to microscopic phenomena involving diffusion, current flow, heat transfer and stress concentration, and elucidate the mechanisms of defect formation.

摩尔定律预测，集成电路中的晶体管数量大约每两年翻一番，几十年来一直是美国经济的主要推动力。不幸的是，与持续的设备缩小相关的技术和基本挑战使得目前的进展速度不可持续。最近，3D集成电路技术已经成为通过堆叠芯片而不是通过缩小器件尺寸来跟上摩尔定律的领先方法。为了实现3D集成，必须开发用于互连和堆叠键合的新连接技术。由于低容量焊料互连具有良好的电气、热和机械性能，因此通过低容量焊料互连进行键合特别有前途。该合作研究奖支持基础研究，以获得开发小批量焊料互连所需的知识。研究结果不仅有助于实现这种新型键合技术在3D集成电路封装中的全部潜力，而且还可用于改善航空航天和核电工业以及电力电子和热管理应用中重要的连接方法。此外，该项目还将帮助这两个来自代表性不足群体的PI之间建立有效的合作。小体积焊料互连的小尺寸使得焊点可以通过形成金属间化合物而以液体焊料为代价等温固化。这种技术也被称为瞬态液相接合，允许在低于预期工作条件的温度下形成接头，从而最大限度地减少过热对电路温度敏感元件的损坏。然而，小体积焊料互连的小尺寸导致操作期间的大电流密度。这些大的电流密度引起大的电、热和机械驱动力，从而引起复杂的微结构过程。本研究旨在推进对小体积焊料互连中复杂微结构工艺的基本理解，特别是关于控制工艺-微结构-性能-性能关系的重要微观机制。该研究团队将开发一个集成的多物理场相场模型，并对小批量焊料互连的加工、操作和损伤过程中的微观结构形成和演变进行系统的模拟研究。模拟将被用来关联宏观工艺参数和操作条件的微观现象，涉及扩散，电流，传热和应力集中，并阐明缺陷形成的机制。