Nanoscale Templated Growth for Integration of Electronic and Photonic Materials

非技术描述：影响我们生活的复杂电子电路和系统从平板电脑和手机到电子游戏和自动驾驶汽车。这些系统是晶体管不断小型化的结果，现在允许超过10亿个晶体管集成在同一个硅芯片上。这种遵循“摩尔定律”的缩放现在已经饱和，并且仅使用传统的Si基材料不再足够。因此，除了Si之外的其他晶体材料必须被集成到芯片上以提供更高的性能并且使得光学器件能够被集成。直接局部结晶沉积是最有可能导致这些不同材料的经济和实用集成的方法。该项目探索了新颖而实用的方法来指导纳米级晶体的形成，从而产生集成许多不同材料的高质量器件和电路。它利用多元化团队的人才，并提供纳米材料加工和表征方面的教育和培训。在传播当今电子系统背后的科学方面所做的努力包括K-12外展和一个涉及所有团队成员的暑期教师培训模块。新的研究成果通过出版物和PI教授的半导体技术课程进行交流，该课程通过南加州大学远程网络提供。技术说明：该项目探索了一种技术，其中Si集成电路晶片作为原子有序的试验板，许多不同种类的晶体材料被集成到纳米级“外延”元素的马赛克中，这些元素在集成系统中执行不同的功能。这项研究建立在异质外延生长可以通过在衬底上形成的有序材料区域（模板）来启动的想法之上。通过在具有足够小的覆盖区的模板上开始生长，即使在高度失配的材料中，也使外延材料中的缺陷最小化，使得失配位错在生长区域的侧面终止。大面积生长通过纳米尺度岛通过横向生长聚结成相干的较大结构而形成。这项研究是通过硅技术中的器件和纳米级图案化的缩放，通过化合物半导体中纳米级活性元素的可行性增加以及使用“模板”来排列沉积的材料来实现的。曾经被认为对成功的器件性能至关重要的长范围（许多微米到毫米）的完美性和有序性已经不那么重要了。相反，该技术的关键是其他基本材料问题，例如结晶材料区域的结构质量、结晶岛相对于衬底标记的准确定位、岛与岛之间的均匀和可控性质以及岛之间的结晶平面的一般对准。该项目利用薄膜外延的最新技术和与局域外延相关的新兴理念，在Si上生产器件质量的III-V材料。该研究将集中在形成无缺陷的高增益区的激光器，可以集成硅光子波导和沟道区的高迁移率晶体管的基础上III-V族化合物半导体在硅衬底上。

Nontechnical Description: Complex electronic circuits and systems that impact our life range from tablet computers and cell phones to electronic games and autonomous vehicles. These systems are a consequence of the relentless miniaturization of transistors that now allows over a billion of them to be integrated on the same silicon chip. This scaling, that has followed 'Moore's Law', has now saturated and the exclusive use of conventional Si-based materials is no longer adequate. Thus, other crystalline materials than Si must be integrated onto the chip to provide higher performance and to enable optical devices to be integrated. Direct localized crystalline deposition is the approach most likely to result in the economical and practical integration of these dissimilar materials. This project explores novel, yet practical, approaches to guide the nanometer scale crystal formation that results in high quality devices and circuits integrating many different materials. It utilizes the talents of a diverse team and provides education and training in nanoscale materials processing and characterizations. The efforts in disseminating the science behind today's electronic systems include K-12 outreach and a summer teacher training module that involves all team members. The new research results are communicated through publications and a semiconductor technology course taught by the PI that is offered over the University of Southern California distance network. Technical Description: This project explores a technology in which a Si integrated circuit wafer acts as an atomically ordered breadboard on which crystalline materials of many different kinds are integrated into a mosaic of nanoscale "epitaxial" elements that perform different functions within an integrated system. The research builds on the idea that hetero-epitaxial growth can be initiated by a region of ordered material formed on a substrate--a template. Defects in the epitaxial material are minimized, even in highly mismatched materials, by initiating the growth on a template with a small enough footprint that misfit dislocations are terminated at the sides of the growth area. Large area growths are formed by the coalescence of the nano-scale islands into a coherent larger structure through lateral growth. The research is enabled by scaling of devices and nanoscale patterning within the Si technology, by the increasing viability of nanoscale active elements in compound semiconductors and the use of 'templates' to arrange the materials being deposited. The long range (many micrometer to mm) perfection and ordering that once was considered essential to successful device performance is less relevant. Instead, the keys to this technology are the other fundamental materials issues such as the structural quality of the crystalline material region, the accurate positioning of the crystalline islands with respect to substrate markers, uniform and controllable properties from island to island, and the general alignment of the crystalline planes among islands. The project exploits the current state of the art in thin film epitaxy and emerging ideas related to local area epitaxy to produce device quality III-V materials on Si. The research will focus on the formation of defect-free high-gain regions for lasers that can be integrated with Si photonic waveguides and channel regions for high mobility transistors based on III-V compound semiconductors on Si substrates.