SBIR Phase I: Analog Stem Cells and Flow for Automated Analog Layout

这个小型企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力是改变模拟设计景观，通过使用数字位置和路由技术创造一种新的模拟布局方式，消除模拟设计瓶颈。潜在的影响是广泛的，包括大多数（如果不是全部的话）半导体公司和设计公司，他们将能够通过利用本提案中开始开发的技术来降低成本和设计进度。数字位置和路线（P和R）技术是一个明显的类比，它现在几乎完全取代了定制的数字设计和布局。除了少数非常专业的利基，数字P和R几乎是每个人在每个芯片上使用的标准工具。该公司的干细胞和血流技术可以成为模拟和混合信号设计技术的等同物。这个小企业创新研究（SBIR）第一阶段项目的目标是流程的几个方面，以证明模拟布局的生产率可以提高几个数量级。一个连续的时间线性均衡器电路布局将创建使用我们的干细胞的位置和路线流，并与手工制作的布局进行比较。通过增加干细胞布局的活跃密度，扩展干细胞库以最大限度地减少映射错误，并分层创建宏，该公司将减少布局引起的寄生，从而使面积、功率和性能达到或超过手工制作的版本。将根据公司的流程生成布局，以证明与放大器或线性均衡器以外的模拟电路的兼容性。此外，该项目将证明从一个铸造工艺到另一个铸造工艺的可移植性，以表明提取后的模拟性能在新工艺中保持不变。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to transform the analog design landscape, eliminating the analog design bottleneck by creating a new way to do analog layout using digital place and route technology. The potential impact is broad and encompasses most, if not all, semiconductor companies and design houses, who will be able to gain reductions in cost and design schedule by utilizing the technology that will begin to be developed in this proposal. The clear analogy is with digital Place and Route (P and R) technology which has now almost completely replaced custom digital design and layout. Except for few very specialized niches, digital P and R is the standard tool used by everyone on nearly every chip. The company's stem cells and flow can become the equivalent of this technology for analog and mixed signal designs. This Small Business Innovation Research (SBIR) Phase I project targets several facets of the flow to prove that analog layout productivity can be increased by orders of magnitude. A continuous time linear equalizer circuit layout will be created using our stem-cell Place and Route flow, and compared to a hand-crafted layout. By increasing the stem-cell layout active density, expanding the stem-cell library to minimize mapping errors, and creating macros hierarchically, the company will reduce layout-induced parasitics such that area, power and performance will match or exceed the handcrafted version. A layout will be generated with the company's flow to prove compatibility with analog circuits other than amplifiers or linear equalizers. Also, the project will prove portability from one foundry process to another to show that post-extraction simulated performance is maintained in the new process.