SBIR Phase I: Analog Stem Cells and Flow for Automated Analog Layout

小型企业创新研究(SBIR)第一阶段项目的更广泛影响/商业潜力是改变模拟设计格局，通过创建一种使用数字布局和布线技术进行模拟布局的新方法来消除模拟设计瓶颈。潜在的影响是广泛的，包括大多数(如果不是全部)半导体公司和设计公司，他们将能够通过利用本提案中将开始开发的技术来减少成本和设计进度。最明显的类比是数字空间和路线(P和R)技术，它现在几乎完全取代了定制的数字设计和布局。除了几个非常专业的利基市场外，数字P和R几乎是每个人在每一块芯片上使用的标准工具。该公司的干细胞和Flow可以成为模拟和混合信号设计的这项技术的等价物。该小型企业创新研究(SBIR)第一阶段项目针对流程的多个方面，以证明模拟布局生产率可以提高数量级。我们将使用干细胞放置和路径流来创建连续时间线性均衡器电路布局，并将其与手工制作的布局进行比较。通过增加干细胞布局活动密度，扩大干细胞库以最大限度地减少映射错误，并分层创建宏，该公司将减少布局引起的寄生，从而使面积、功率和性能与手工制作的版本相匹配或超过。将根据该公司的流程生成版图，以证明与放大器或线性均衡器以外的模拟电路的兼容性。此外，该项目将证明从一个铸造工艺到另一个工艺的可移植性，以表明在新工艺中保持了提取后的模拟性能。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to transform the analog design landscape, eliminating the analog design bottleneck by creating a new way to do analog layout using digital place and route technology. The potential impact is broad and encompasses most, if not all, semiconductor companies and design houses, who will be able to gain reductions in cost and design schedule by utilizing the technology that will begin to be developed in this proposal. The clear analogy is with digital Place and Route (P and R) technology which has now almost completely replaced custom digital design and layout. Except for few very specialized niches, digital P and R is the standard tool used by everyone on nearly every chip. The company's stem cells and flow can become the equivalent of this technology for analog and mixed signal designs. This Small Business Innovation Research (SBIR) Phase I project targets several facets of the flow to prove that analog layout productivity can be increased by orders of magnitude. A continuous time linear equalizer circuit layout will be created using our stem-cell Place and Route flow, and compared to a hand-crafted layout. By increasing the stem-cell layout active density, expanding the stem-cell library to minimize mapping errors, and creating macros hierarchically, the company will reduce layout-induced parasitics such that area, power and performance will match or exceed the handcrafted version. A layout will be generated with the company's flow to prove compatibility with analog circuits other than amplifiers or linear equalizers. Also, the project will prove portability from one foundry process to another to show that post-extraction simulated performance is maintained in the new process.