SBIR Phase II: Analog/Mixed-Signal Integrated Circuit Verification Coverage

SBIR 第二阶段：模拟/混合信号集成电路验证覆盖范围

• 批准号: 1431022
• 负责人: Felicia James
• 金额: $ 75万
• 依托单位: Zipalog, Inc.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-10-01 至 2019-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1431022&HistoricalAwards=false
• 关键词: SBIR; Phase; II; Analog; Mixed

The broader impact/commercial potential of this project is to increase the competitiveness of U.S. semiconductor industry by improving the quality of A/MS design verification, improving first pass design success and reducing time-to-market. Today, current analog verification methods and tools often fail to catch design mistakes, especially due to unforeseen interactions across chip subsystems, and these mistakes are a frequent cause of costly delays in bringing products to market even on chips where analog is only a small portion of the overall design ? a $63 billion market. The costs and lost profit potential related to multiple design versions can quickly run to millions of dollars and easily dwarfs the cost of providing designers access to the appropriate design tools. Using two different market analyses, the first using a digital verification market analogy and the second considering worldwide new (not slight derivatives) designs in just the AMS IC market, leads to an estimation of total available market for new analog verification solutions of $300 million annual revenue. Further extending the verification solutions with analytics and collaboration tools can potentially increase the market by a further 50% to $450 million annual revenue. Understanding A/MS verification coverage is a key component of this opportunity.This Small Business Innovation Research (SBIR) Phase 2 project proposes a verification coverage system for analog/mixed-signal (A/MS) integrated circuit development. Verification of today?s complex integrated circuits and systems is widely acknowledged as a critical challenge to improving design productivity. Part of the verification challenge revolves around understanding what portion of the operating space has been examined; i.e., ?covered?. Today well-accepted formal and simulation-based techniques exist to capture and measure test coverage for digital integrated circuits, but there is no corresponding commercial capability for analog and mixed-signal integrated circuits. Analog designers frequently spend too much time analyzing and over-testing system behavior for a small set of well understood usage scenarios while leaving significant portions of the state-space completely untested. The design exploration problem for A/MS circuits presents a critical challenge for implementing such systems due to the inherently large design space associated with these types of circuits. Key objectives for the project include productizing and extending key components demonstrated in the Phase 1 prototype. This project will deliver a commercial product to provide A/MS verification coverage data that is actionable and facilitates collaboration between design and verification teams. The resulting product will have scalability and performance to handle large complex designs.

该项目更广泛的影响/商业潜力是通过提高 A/MS 设计验证的质量、提高首次通过设计成功率和缩短上市时间来提高美国半导体行业的竞争力。如今，当前的模拟验证方法和工具常常无法发现设计错误，特别是由于芯片子系统之间不可预见的相互作用，这些错误是导致产品上市延迟成本高昂的常见原因，即使是在模拟仅占整体设计一小部分的芯片上？ 630亿美元的市场。与多个设计版本相关的成本和潜在利润损失可能很快就会达到数百万美元，并且很容易使设计人员获得适当设计工具的成本相形见绌。使用两种不同的市场分析，第一种使用数字验证市场类比，第二种仅考虑 AMS IC 市场中的全球新（非轻微衍生）设计，从而估计新模拟验证解决方案的总可用市场年收入为 3 亿美元。通过分析和协作工具进一步扩展验证解决方案可能会使市场进一步增加 50%，年收入达到 4.5 亿美元。了解 A/MS 验证覆盖范围是这一机会的关键组成部分。这个小型企业创新研究 (SBIR) 第 2 阶段项目提出了一个用于模拟/混合信号 (A/MS) 集成电路开发的验证覆盖系统。当今复杂的集成电路和系统的验证被广泛认为是提高设计生产力的关键挑战。验证挑战的一部分围绕着了解操作空间的哪一部分已被检查；即“覆盖”。如今，已经存在广为接受的形式和基于仿真的技术来捕获和测量数字集成电路的测试覆盖率，但模拟和混合信号集成电路没有相应的商业能力。模拟设计人员经常花费太多时间来分析和过度测试一小部分易于理解的使用场景的系统行为，同时使状态空间的很大一部分完全未经测试。由于与这些类型的电路相关的固有的大设计空间，A/MS 电路的设计探索问题对实现此类系统提出了严峻的挑战。该项目的主要目标包括产品化和扩展第一阶段原型中演示的关键组件。该项目将提供商业产品，以提供可操作的 A/MS 验证覆盖率数据，并促进设计和验证团队之间的协作。由此产生的产品将具有可扩展性和性能来处理大型复杂设计。