CAREER: New Foundations for Next-Generation Reliable Throughput Architecture Design

随着对提高性能和能效的需求，包括非易失性存储器（如自旋传递扭矩RAM (STT-RAM)）、3D集成技术（3D）和近阈值电压计算（NTC）在内的新技术越来越多地应用于最先进的吞吐量处理器中。由于这些新技术不是为可靠计算而设计的，因此可靠性挑战已经成为传统吞吐量架构设计中的一个关键问题，成为将它们集成到下一代吞吐量处理器中的主要障碍。迫切需要研究能够利用吞吐量处理器的独特功能来表征和提高下一代基于新技术的吞吐量架构设计的可靠性的创新技术。吞吐量处理器中最重要的可靠性挑战包括粒子撞击引起的软错误、老化效应引起的硬错误和制造工艺变化。主要研究者正在为脆弱性表征和预测、错误检测和容错建立新的基础，以应对吞吐量处理器中与新技术集成的主要可靠性挑战。项目目标包括：(1)建模和分析新技术（例如，STT-RAM， NTC和3D）启用吞吐量处理器在存在软错误，老化效应和工艺变化的情况下的脆弱性；(2)建立快速准确的预测模型，预测新技术下吞吐量处理器的漏洞阶段行为；(3)开发轻量级错误检测机制；(4)探索新技术带来的机遇和挑战，以经济有效地容忍下一代吞吐量架构设计中的各种类型的错误。提出的研究将大大提高在CMOS之外的未来技术中构建可靠吞吐量处理器的能力，使其能够在不遭受各种故障机制造成的负面影响的情况下满足摩尔定律。此外，该项目将实现吞吐量处理器应用于从移动计算到云计算的广泛计算规模的愿望，并增加吞吐量处理器的部署，以支持科学和工程（例如金融，医学，生物，石油，航空航天和地质）的超级计算。该项目还将通过吸引少数族裔院校的高中生和本科生参与研究，扩展计算机工程课程，包括吞吐量处理器的可靠性建模和优化技术，吸引女性和代表性不足的群体接受研究生教育，以及为美国IT劳动力的教育和培训传播研究基础设施，从而为社会做出贡献。

With the demand on improving performance and energy-efficiency, novel technologies including non-volatile memory (e.g., spin-transfer torque RAM (STT-RAM)), 3D integration technology (3D), and near-threshold voltage computing (NTC) have been increasingly deployed in the state-of-the-art throughput processors. Since the novel technologies are not designed for dependable computing, the reliability challenges, which have been a crucial issue in conventional throughput architecture design, become the major obstacle for integrating them into next-generation throughput processors. There is a pressing need for the investigation of innovative techniques that are able to take advantage of throughput processors' unique features for characterizing and improving the reliability of the next-generation new-technology based throughput architecture design. The paramount reliability challenges in throughput processors include particle strikes induced soft errors, hard errors driven by aging effects, and manufacturing process variations. The principle investigator is building new foundations for vulnerability characterization and prediction, error detection, and fault tolerance against those dominant reliability challenges in throughput processors integrated with novel technologies. The project objectives include: (1) modeling and analyzing the vulnerability of novel-technology (e.g., STT-RAM, NTC, and 3D) enabled throughput processors in the presence of soft error, aging effects, and process variations; (2) fast and accurate predictive model to forecast the vulnerability phase behavior of throughput processors under new technologies; (3) developing the light-weight error detection mechanisms; and (4) exploring the opportunities and challenges introduced by the novel technologies to cost-effectively tolerate various types of errors in next-generation throughput architecture design. The proposed research will significantly promote the capability of architecting reliable throughput processors in future technologies beyond CMOS, making it possible to fulfill the Moore's Law without suffering the negative effects caused by various fault mechanisms. Moreover, this project will realize the desire of applying throughput processors into a wide range of computing scale from mobile computing to cloud computing, and increasing the deployment of throughput processors in support of supercomputing in science and engineering (e.g., finance, medical, biology, petroleum, aerospace, and geology). This project will also contribute to society through engaging high-school and undergraduate students from minority-serving institutions into research, expanding the computer engineering curriculum with reliability modeling and optimization techniques on throughput processors, attracting women and under-represented groups into graduate education, and disseminating research infrastructure for education and training of US IT workforce.