CAREER: New Foundations for Next-Generation Reliable Throughput Architecture Design

随着对提高性能和能量效率的需求，包括非易失性存储器（例如，自旋转移矩RAM（STT-RAM））、3D集成技术（3D）和近阈值电压计算（NTC）已经越来越多地部署在现有技术的吞吐量处理器中。由于新技术不是为可靠计算而设计的，可靠性挑战，这一直是传统吞吐量架构设计中的关键问题，成为将它们集成到下一代吞吐量处理器中的主要障碍。有一个迫切需要的调查创新技术，能够利用吞吐量处理器的独特功能，表征和提高下一代新技术的吞吐量架构设计的可靠性。吞吐量处理器中最重要的可靠性挑战包括粒子撞击引起的软错误、老化效应驱动的硬错误以及制造工艺变化。主要研究者正在建立新的基础，脆弱性表征和预测，错误检测，容错对那些主要的可靠性挑战，在吞吐量处理器集成新技术。该项目的目标包括：（1）建模和分析新技术的脆弱性（例如，STT-RAM、NTC和3D）在存在软错误、老化效应和工艺变化的情况下使吞吐量处理器能够工作：（2）快速准确的预测模型来预测吞吐量处理器在新技术下的脆弱性阶段行为：（3）开发轻量级错误检测机制;以及（4）探索由新技术引入的机遇和挑战，以在下一代吞吐量架构设计中经济有效地容忍各种类型的错误。建议的研究将显着促进架构可靠的吞吐量处理器在未来的技术超越CMOS的能力，使之有可能满足摩尔定律，而不会遭受各种故障机制所造成的负面影响。而且，该项目将实现将吞吐量处理器应用于从移动的计算到云计算的广泛计算规模的愿望，并增加吞吐量处理器的部署以支持科学和工程中的超级计算（例如，金融、医学、生物学、石油、航空航天和地质学）。该项目还将通过让少数民族服务机构的高中和本科生参与研究，扩大计算机工程课程，增加吞吐量处理器的可靠性建模和优化技术，吸引女性和代表性不足的群体接受研究生教育，以及传播美国IT劳动力教育和培训的研究基础设施，为社会做出贡献。

With the demand on improving performance and energy-efficiency, novel technologies including non-volatile memory (e.g., spin-transfer torque RAM (STT-RAM)), 3D integration technology (3D), and near-threshold voltage computing (NTC) have been increasingly deployed in the state-of-the-art throughput processors. Since the novel technologies are not designed for dependable computing, the reliability challenges, which have been a crucial issue in conventional throughput architecture design, become the major obstacle for integrating them into next-generation throughput processors. There is a pressing need for the investigation of innovative techniques that are able to take advantage of throughput processors' unique features for characterizing and improving the reliability of the next-generation new-technology based throughput architecture design. The paramount reliability challenges in throughput processors include particle strikes induced soft errors, hard errors driven by aging effects, and manufacturing process variations. The principle investigator is building new foundations for vulnerability characterization and prediction, error detection, and fault tolerance against those dominant reliability challenges in throughput processors integrated with novel technologies. The project objectives include: (1) modeling and analyzing the vulnerability of novel-technology (e.g., STT-RAM, NTC, and 3D) enabled throughput processors in the presence of soft error, aging effects, and process variations; (2) fast and accurate predictive model to forecast the vulnerability phase behavior of throughput processors under new technologies; (3) developing the light-weight error detection mechanisms; and (4) exploring the opportunities and challenges introduced by the novel technologies to cost-effectively tolerate various types of errors in next-generation throughput architecture design. The proposed research will significantly promote the capability of architecting reliable throughput processors in future technologies beyond CMOS, making it possible to fulfill the Moore's Law without suffering the negative effects caused by various fault mechanisms. Moreover, this project will realize the desire of applying throughput processors into a wide range of computing scale from mobile computing to cloud computing, and increasing the deployment of throughput processors in support of supercomputing in science and engineering (e.g., finance, medical, biology, petroleum, aerospace, and geology). This project will also contribute to society through engaging high-school and undergraduate students from minority-serving institutions into research, expanding the computer engineering curriculum with reliability modeling and optimization techniques on throughput processors, attracting women and under-represented groups into graduate education, and disseminating research infrastructure for education and training of US IT workforce.