SHF:Small:Collaborative Research:Exploring Energy-Efficient GPGPUs Through Emerging Technology Integration

如今，图形处理单元（gpu）已被广泛用于通用计算，并被称为gpgpu。然而，当前和未来的gpgpu面临的主要制约因素是功率和能量。由于特征尺寸的缩小和对大规模并行计算核心的需求以提高吞吐量，单个GPU芯片上集成的晶体管数量不断增加。另一方面，由于泄漏限制，每个新技术节点晶体管供电电压的持续下降在很大程度上已经停滞，导致功率密度不断增加。因此，未来的gpgpu必须变得更加节能，以避免撞墙。为了满足对性能和能效日益增长的需求，非易失性存储器、银行间隧道场效应晶体管（tfet）、硅纳米光子学和三维（3D）集成等新兴技术正在硬件设计中得到应用，并有望以前所未有的规模实现功率效率。研究人员正在探索一个协同项目，通过新兴技术的整合，从整体上和层次上提高GPGPU的能源效率。项目目标包括：(1)GPU计算核心中的非易失性存储器和低功耗机制，大幅降低泄漏和动态功耗；(2)混合TFET-CMOS（互补金属氧化物半导体）方法，有效解决核内和核间能级的能量挑战；(3)基于硅纳米光子学技术的3d堆叠吞吐量架构，在提高存储器访问性能的同时降低功耗；(4)整合重点研究创新和跨技术优化，充分挖掘这些新兴技术所带来的GPGPU设计潜力。该研究将促进gpgpu保持在深亚微米尺度的轨道上，并满足对高性能计算日益增长的需求，因此将有利于许多现实生活中的应用。该项目还将通过吸引少数族裔院校的高中生和本科生参与研究、吸引女性和其他代表性不足的群体进入研究生教育、利用GPGPU功率建模和优化技术扩展计算机工程课程、传播用于教育和培训的研究基础设施，以及与GPU研发行业合作，为社会做出贡献。

Nowadays, graphics processing units (GPUs) have been widely adopted for general-purpose computing, and are known as GPGPUs. However, current and future GPGPUs confront power and energy as the dominant constraints. The number of transistors integrated on a single GPU chip continues to increase due to shrinking feature size and the demand for massively parallel computing cores to increase throughput. On the other hand, the continuous decrease of transistor supply voltage at each new technology node has largely stalled because of leakage constraints, leading to an ever-increasing power density. Therefore, future GPGPUs must become more inherently energy efficient to avoid hitting the power wall. To meet the increasing demands on performance and energy-efficiency, emerging technologies such as non-volatile memory, inter-bank tunneling field effect transistors (TFETs), silicon nanophotonics, and three-dimensional (3D) integration are being deployed in hardware design and promise realization of power efficiency at a scale never expected before. The investigators are exploring a synergetic program to holistically and hierarchically improve the GPGPU's energy efficiency through emerging technology integration. The project objectives include (1) non-volatile memory in the GPU computing cores and low-power mechanisms to substantially reduce leakage and dynamic power consumption; (2) a hybrid TFET-CMOS (complementary metal-oxide semiconductor) methodology to effectively address the energy challenge at both intra- and inter-core levels; (3) a novel 3D-stacked throughput architecture based on silicon-nanophotonics technology to improve memory access performance yet reduce power consumption; (4) integration of the key research innovations and cross-technology optimizations to fully explore the potential of GPGPU design enabled by these emerging technologies. The proposed research will facilitate GPGPUs staying on track with deep sub-micron scaling and meeting the increasing demand for high-performance computing, and will hence benefit numerous real-life applications. This project will also contribute to society through engaging high-school and undergraduate students from minority-serving institutions in research, attracting women and other under-represented groups into graduate education, expanding the computer engineering curriculum with GPGPU power modeling and optimization techniques, disseminating research infrastructure for education and training, and collaborating with the GPU R&D industry.