EAGER: Collaborative Research: Memristive Accelerator for Extreme Scale Linear Solvers

物理系统的计算机模型是现代科学和工程研究与开发的重要组成部分。地球的大规模计算模型？天气、气候和地质活动；；生物系统模型；星系的天文模型；甚至宏观经济模型也需要大量的计算资源。这些模拟一次在数千个处理器上运行几个月，在完成之前使用了数千万或数亿个CPU小时。该项目采用了一种全新的方法来设计和实现下一代百亿亿次超级计算，利用传统集成电路技术和新兴的电阻随机存取存储器（RRAM）设备的最新发展。该项目的目标是加速大型线性系统的求解器，这是现代科学计算的支柱。在这个项目中，一组新的数字和模拟硬件原语与一类利用所提出的加速器的新算法共同设计。一个小规模的原型正在通过EAGER项目进行设计、制造和测试，以证明基本构建模块的可行性。RRAM是一种非易失性存储技术，它避免了静态和动态随机存取存储器（SRAM和DRAM）的可扩展性挑战，是一种有前途的“通用存储器”候选者，其读取速度与SRAM和DRAM一样快，密度与FLASH存储器相当。除了简单地依靠RRAM进行存储之外，该项目还集成了电路、架构和算法层面的创新，以开发一种质量上新的硬件加速器，其每瓦性能比传统数字计算机高几个数量级。基于数字忆阻器的电路通过在整个数据集上并行执行按位矩阵向量乘法来避免数据移动。模拟硬件快速地为迭代求解器提供准确的初始种子，其中无误差数字电路改进初始估计以解决线性方程系统。一种新颖的迭代求解器算法独特地适应了所提出的硬件，补偿了模拟电路引入的不准确性和随机变化，通过少量的数字迭代系统地减少了误差。这种数字计算和模拟忆阻电路的结合，在高密度RRAM配置中，有望对高性能计算产生革命性的影响。正在研究的系统有可能将执行时间从几个月缩短到几个小时，从而解决迄今为止现代高性能计算系统无法解决的科学问题。该项目汇集了计算机体系结构、高性能集成电路设计、数值算法和科学计算方面的研究人员，以完成这项多学科的努力。算法、架构和电路级的创新正在通过发表的论文以及关于仿真工具的教程传播到更广泛的研究社区。该项目的教育部分包括：1)对学生进行VLSI、架构和优化方面的培训；2)将电阻式记忆纳入建筑与电路课程。这些pi还亲自参与当地的项目，促进妇女和未被充分代表的少数民族参与计算机科学和工程，并将开始努力增加当地少数民族在罗切斯特大学CS和ECE项目中的入学率。

Computer models of physical systems are a vital part of modern scientific and engineering research and development. Large scale computational models of the Earth?s weather, climate, and geological activity; models of biological systems; astronomical models of galaxies; and even macroeconomic models require immense computing resources. These simulations run on many thousands of processors for several months at a time, utilizing tens or hundreds of millions of CPU hours before completion. This project takes a radically new approach to the design and implementation of next generation, exascale supercomputing by leveraging recent developments at the intersection of conventional integrated circuit technology, and emerging resistive random access memory (RRAM) devices. The goal of this project is the acceleration of solvers for large linear systems, which form the backbone of modern scientific computing. In this project a novel set of digital and analog hardware primitives is co-designed with a new class of algorithms that exploit the proposed accelerator. A small-scale prototype is being designed, fabricated, and tested through the EAGER program to demonstrate the feasibility of the fundamental building blocks. RRAM is a non-volatile memory technology that avoids the scalability challenges of static and dynamic random access memories (SRAM and DRAM), and is a promising "universal memory" candidate, offering read speeds as fast as SRAM and DRAM, and densities comparable to FLASH memory. Beyond simply relying on RRAM for storage, the project integrates circuit, architecture, and algorithm level innovations in developing a qualitatively new hardware accelerator with orders of magnitude greater performance per watt than classical digital computers. Digital memristor-based circuits avoid data movement by performing bitwise matrix vector multiplication in parallel across an entire dataset. Analog hardware quickly provides an accurate, initial seed to an iterative solver, wherein error free digital circuits refine the initial estimate to solve a system of linear equations. A novel, iterative solver algorithm uniquely adapted to the proposed hardware compensates for the inaccuracies and random variations introduced by the analog circuits, systematically reducing the error through a small number of digital iterations. This combination of digital computation and analog memristor circuits, within high-density RRAM configurations, is expected to have a transformative effect on high performance computing. The system under investigation has the potential to reduce execution time from months to hours, enabling solutions to scientific problems heretofore beyond the reach of modern HPC systems. The project brings together researchers in computer architecture, high performance integrated circuit design, numerical algorithms, and scientific computing to accomplish this multi-disciplinary effort. Algorithm, architecture, and circuit level innovations are being disseminated to the broader research community through published papers, as well as tutorials on the simulation tools. The educational component of the project involves 1) training students in VLSI, architecture, and optimization; and 2) incorporating resistive memories into the architecture and circuits curricula. The PIs are also personally involved in local programs promoting the participation of women and underrepresented minorities in computer science and engineering, and will initiate an effort to increase the enrollment of local minorities in the University of Rochester CS and ECE programs.