EAGER: Collaborative Research: Memristive Accelerator for Extreme Scale Linear Solvers

物理系统的计算机模型是现代科学和工程研究与发展的重要组成部分。地球的大规模计算模型？地球的天气、气候和地质活动;生物系统的模型;星系的天文模型;甚至宏观经济模型都需要巨大的计算资源。这些模拟每次在数千个处理器上运行数月，在完成之前使用数千万或数亿个CPU小时。该项目采取了一种全新的方法来设计和实现下一代，亿亿级超级计算，利用传统集成电路技术和新兴电阻式随机存取存储器（RRAM）器件的交叉点的最新发展。该项目的目标是加速大型线性系统的求解器，这些系统构成了现代科学计算的支柱。 在这个项目中，一组新的数字和模拟硬件原语的协同设计与一类新的算法，利用建议的加速器。一个小规模的原型正在设计，制造，并通过EAGER计划进行测试，以证明基本构建模块的可行性。 RRAM是一种非易失性存储器技术，避免了静态和动态随机存取存储器（SRAM和DRAM）的可扩展性挑战，是一种有前途的“通用存储器”候选者，提供与SRAM和DRAM一样快的读取速度，以及与闪存相当的密度。除了简单地依靠RRAM进行存储外，该项目还集成了电路、架构和算法级创新，开发了一种全新的硬件加速器，其每瓦性能比传统数字计算机高出几个数量级。 基于数字忆阻器的电路通过跨整个数据集并行执行按位矩阵向量乘法来避免数据移动。模拟硬件快速地向迭代求解器提供准确的初始种子，其中无误差数字电路细化初始估计以求解线性方程组。一种新颖的，迭代求解器算法，唯一适用于所提出的硬件补偿模拟电路引入的不准确性和随机变化，通过少量的数字迭代系统地减少了错误。在高密度RRAM配置中，数字计算和模拟忆阻器电路的这种组合预计将对高性能计算产生变革性影响。正在研究的系统有可能将执行时间从数月减少到数小时，从而解决迄今为止现代HPC系统无法解决的科学问题。 该项目汇集了计算机体系结构，高性能集成电路设计，数值算法和科学计算的研究人员，以完成这一多学科的努力。 算法，架构和电路级的创新正在传播到更广泛的研究社区通过发表论文，以及仿真工具的教程。该项目的教育部分包括：1）培训学生在超大规模集成电路，架构和优化; 2）将电阻存储器纳入架构和电路课程。PI还亲自参与促进妇女和代表性不足的少数民族参与计算机科学和工程的地方方案，并将努力增加当地少数民族在罗切斯特大学CS和ECE方案的入学率。

Computer models of physical systems are a vital part of modern scientific and engineering research and development. Large scale computational models of the Earth?s weather, climate, and geological activity; models of biological systems; astronomical models of galaxies; and even macroeconomic models require immense computing resources. These simulations run on many thousands of processors for several months at a time, utilizing tens or hundreds of millions of CPU hours before completion. This project takes a radically new approach to the design and implementation of next generation, exascale supercomputing by leveraging recent developments at the intersection of conventional integrated circuit technology, and emerging resistive random access memory (RRAM) devices. The goal of this project is the acceleration of solvers for large linear systems, which form the backbone of modern scientific computing. In this project a novel set of digital and analog hardware primitives is co-designed with a new class of algorithms that exploit the proposed accelerator. A small-scale prototype is being designed, fabricated, and tested through the EAGER program to demonstrate the feasibility of the fundamental building blocks. RRAM is a non-volatile memory technology that avoids the scalability challenges of static and dynamic random access memories (SRAM and DRAM), and is a promising "universal memory" candidate, offering read speeds as fast as SRAM and DRAM, and densities comparable to FLASH memory. Beyond simply relying on RRAM for storage, the project integrates circuit, architecture, and algorithm level innovations in developing a qualitatively new hardware accelerator with orders of magnitude greater performance per watt than classical digital computers. Digital memristor-based circuits avoid data movement by performing bitwise matrix vector multiplication in parallel across an entire dataset. Analog hardware quickly provides an accurate, initial seed to an iterative solver, wherein error free digital circuits refine the initial estimate to solve a system of linear equations. A novel, iterative solver algorithm uniquely adapted to the proposed hardware compensates for the inaccuracies and random variations introduced by the analog circuits, systematically reducing the error through a small number of digital iterations. This combination of digital computation and analog memristor circuits, within high-density RRAM configurations, is expected to have a transformative effect on high performance computing. The system under investigation has the potential to reduce execution time from months to hours, enabling solutions to scientific problems heretofore beyond the reach of modern HPC systems. The project brings together researchers in computer architecture, high performance integrated circuit design, numerical algorithms, and scientific computing to accomplish this multi-disciplinary effort. Algorithm, architecture, and circuit level innovations are being disseminated to the broader research community through published papers, as well as tutorials on the simulation tools. The educational component of the project involves 1) training students in VLSI, architecture, and optimization; and 2) incorporating resistive memories into the architecture and circuits curricula. The PIs are also personally involved in local programs promoting the participation of women and underrepresented minorities in computer science and engineering, and will initiate an effort to increase the enrollment of local minorities in the University of Rochester CS and ECE programs.