NeTS: CSR: Medium: Collaborative Research: Wireless Datacenter-on-Chip (WiDoC): A New Paradigm for Big Data Computing

该项目专注于大数据计算的新范式，即由数千个核心组成的芯片上数据中心（DoC），可以运行计算和数据密集型应用程序，与现有平台相比，效率提高了几个数量级。事实上，如今的数据中心和高性能计算集群主要受到功率、散热和面积的限制；它们占据很大的空间，需要复杂的冷却机制来维持所需的性能水平。相比之下，该项目依赖于新兴的多核处理器，这些处理器可以运行大数据应用程序，同时为必要的功耗/性能/热权衡提供系统资源。因此，各种大数据应用程序，如社会计算、生命科学、网络或娱乐，都可以从这种旨在从手持设备实现服务器级性能的新设计范式中受益匪浅。所提出的工作为网络系统设计引入了一个新的方向，该方向是由新兴的无线片上互连范例实现的。实际上，实现DoC级别的大规模集成需要在多个抽象级别上进行重大创新，从片上网络和相关物理层的设计，一直到各种应用程序的映射和运行时管理。为此，研究目标包括：-设计一个小世界无线网络架构，作为多核无线DoC （WiDoC）的通信骨干-设计适合低延迟数据通信的高集成3D无线DoC的物理层方法-评估与相关大数据应用的拟议WiDoC平台的各种延迟-功率-热（LPT）权衡。虽然之前的大多数工作都考虑了通过有线链路进行通信的2D多核平台，但该提案通过3D小世界网络架构重新定义了片上通信的基础，该架构在平面层中具有次太赫兹无线链路，并在垂直方向上具有基于电感耦合的无线接口；这允许充分的灵活性和重新配置，使此类平台适合以前所未有的能效水平处理大数据应用。所提出的研究是独特的，因为它汇集了来自片上网络（NoC），无线和复杂网络，通信电路和优化技术的高度新颖和跨学科的概念，旨在实现数据中心规模性能的单芯片解决方案。这项工作的教育贡献将有助于建立一个跨学科的研究型课程，用于高性能多核心系统设计，旨在增加吸引到这一工程领域的学生人数。

This project focuses on a new paradigm for Big Data computing, namely a Datacenter-on-a-Chip (DoC) consisting of thousands of cores that can run compute- and data-intensive applications, orders of magnitude more efficiently compared to existing platforms. Indeed, nowadays data centers and high performance computing clusters are dominated by power, thermal, and area constraints; they occupy large spaces and necessitate sophisticated cooling mechanisms to sustain the required performance levels. In contrast, this project relies on emerging many-core processors that can run Big Data applications while provisioning the system resources for the necessary power/performance/thermal trade-offs. Consequently, various big data applications like social computing, life sciences, networking, or entertainment, can benefit immensely from this new design paradigm that aims at achieving server-scale performance from hand-held devices.The proposed work introduces a new direction in networked system design enabled by the emerging wireless on-chip interconnect paradigm. Indeed, achieving DoC level of massive integration requires significant innovation at multiple levels of abstraction, ranging from the design of the on-chip network and associated physical layer, all the way to mapping and runtime management of various applications. To this end, the research goals include:- Design of a small-world wireless network architecture as a communication backbone for manycore-enabled wireless DoC (WiDoC) - Design methods at physical layer for highly-integrated 3D wireless DoC suitable for low latency data communication - Evaluation of various latency-power-thermal (LPT) trade-offs for the proposed WiDoC platform with relevant big data applications.While most of the prior work considers 2D many-core platforms where communication happens through wired links, this proposal redefines the very foundations of on-chip communication via 3D small-world network architecture with sub-THZ wireless links in the planar layers and inductive coupling-based wireless interfaces in the vertical direction; this allows for full flexibility and reconfiguration and makes such platforms suitable for processing big data applications at unprecedented levels of energy efficiency.The proposed research is unique as it brings together highly novel and interdisciplinary concepts from network-on-chip (NoC), wireless, and complex networks, communication circuits, and optimization techniques aimed at single chip solutions for achieving data center-scale performance. The educational contribution of this work will help establishing an interdisciplinary research-based curriculum for high performance many-core system design meant to increase the number of students attracted to this area of engineering.