SHF: Small: The Chip Is the Network: Rethinking the Theoretical Foundations of Multicore Architecture Design

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Project ID: 0916752 Title: The Chip Is the Network: Rethinking the Theoretical Foundations of Multicore Architecture DesignPI Name: Radu MarculescuInstitution: Carnegie-Mellon UniversityABSTRACTRecent advances in CMOS technology allow the integration of tens or hundreds of individually programmable processing elements, together with large amounts of dedicated memory, on the same system-on-chip (SoC). In such multiprocessor systems, individual processing nodes can communicate and coordinate via networks-on-chip (NoCs). Therefore, a major challenge is to determine the mathematical techniques for designing and optimizing such on-chip networks in a rigorous manner. Traditional queuing and Markov chain approaches to buffer allocation are helpful to a certain extent, but capturing the traffic variability represents a major problem. Starting from these overarching ideas, this project introduces a new statistical-physics approach for performance analysis in multiprocessor SoCs. More precisely, we develop a completely new mathematical description of network traffic using an analogy between a Bose gas and the information flow in the communication network. This new modeling paradigm where networks are seen as gases can be further used to develop efficient on-chip buffer assignment algorithms. The new design methodology enables the development of more efficient multiprocessor SoCs which have a dramatic impact on society via applications ranging from entertainment to gaming to security and to bio- and gene engineering. More broadly, the results of this project impact significantly other research communities by improving the level of understanding of networking concepts needed to design and control complex systems.