Design Methods and Optimization Techniques for Multiprocessor Systems-on-Chip (MPSoCs)

项目编号：0 702420项目名称：多处理器片上系统（MPSoC）的设计方法和优化技术PI姓名：Radu Marculescu机构：卡内基梅隆大学摘要纳米级设计的电子集成系统将很快在单个芯片上包含十亿个晶体管。这使得集成数百个IP核同时运行多个应用成为可能。然而，随着CMOS技术接近纳米级域，增加的功耗、通信中缺乏可扩展性以及在如此小的尺寸下的设计的可靠性使得使用现有的设计方法和软件工具来构建负担得起的多处理器片上系统（MPSoC）变得不切实际。因此，本计画将探讨以通讯为基础的设计，作为未来多芯片系统的设计范例。更确切地说，我们提出了自动化的通信架构合成的应用特定的片上网络（NoCs），其中许多异构IP核通过分组交换进行通信，类似于最常用的技术在互联网上。我们的NoC方法背后的主要承诺是为片上通信实现真正可扩展和节能的解决方案，同时保持可管理的设计工作，因为摩尔定律年复一年地继续增加芯片的复杂性。

Project ID: 0 702420Project Title: Design Methods and Optimization Techniques for Multiprocessor Systems-on-Chip (MPSoCs)PI Name: Radu MarculescuInstitution: Carnegie Mellon UniversityABSTRACTElectronic integrated systems designed at nanoscale will soon contain a billion transistors on a single chip. This makes it possible to integrate hundreds of IP cores running multiple applications simultaneously. However, as CMOS technology approaches the nanoscale domain, increased power consumption, lack of scalability in communication, and reliability of the design at such small sizes make it impractical to build affordable multiprocessor systems-on-chip (MPSoCs) using the existing design methodologies and software tools. Consequently, this project explores the communication-based design as a new paradigm to design the future MPSoCs. More precisely, we propose automated communication architecture synthesis for application-specific Networks-on-Chip (NoCs) where many heterogeneous IP cores communicate via packet switching, similarly to techniques used most commonly over the Internet. The main promise behind our NoC approach is to achieve a truly scalable and energy-efficient solution for on-chip communication, while maintaining manageable design efforts as Moore's law continues to increase chip complexity year after year.