SHF: Small: DeSCPar: Decoupled Supply-Compute Communication Management for Heterogeneous, Accelerator-Oriented Parallelism

在过去的十年里，摩尔定律和Dennard伸缩的减速要求计算向使用片上并行进行戏剧性的转变，以便在可接受的功率预算下实现计算机系统的性能伸缩。除此之外，系统还大幅增加了对异类处理元件和专用加速器的使用。这种面向加速器的异类并行的大部分复杂性都暴露在程序员和编译器编写人员没有足够的抽象的情况下。因此，要实现高性能，程序通常需要包括详细的、特定于平台的定制，特别是在数据在内存和计算元素之间移动以及从一个计算元素移动到另一个计算元素时的分段。这种特定于平台的定制限制了这类程序的可移植性；当发布新的芯片实现时，通常需要大量的软件返工才能恢复这种高性能。总体而言，结果是异类并行正在降低应用软件的性能可移植性。DeSCPar的研究解决了这个问题，并代表了在提高可编程性方面的重要研究。开发的工具将作为自由软件分发，包括DeSCPar模拟器和设计工具。此外，该项目还包括一系列围绕提高计算劳动力多样性的活动。DeSCPar方法使用去耦合的供应-计算并行来在高度并行、高度异质的系统上实现可移植的性能。受分离的访问-执行方法的启发，DeSCPar同样将值计算与“供给”它们的内存访问和地址计算分离。通过使用自动切片技术将代码分割为数据提供部分和计算部分，可以实现高性能的内存优化，同时保持高级别的应用程序可移植性。在DeSCPar中，值计算操作的目标是在CompD上运行，该CompD可以是硬件加速器、专门优化的CPU或通用CPU。同样，内存供应代码针对的是SuppD，它可以针对其任务进行专门优化。通过使用SuppD和CompD单元的不同组合，可以构建丰富的异质系统，并且软件可以自动映射到这些系统上。本项目：(I)提出并原型自动编译技术(基于LLVM)用于切片和优化DeSCPar代码；以及(Ii)提出并评估基于DeSCPar组织结构的硬件设计优化。

Over the past decade, the deceleration of Moore's Law and Dennard Scaling has required computing to make a dramatic shift towards the use of on-chip parallelism in order to achieve computer systems performance scaling at acceptable power budgets. Beyond that, systems have also dramatically increased their use of heterogeneous processing elements and specialized accelerators. Much of the complexity of this heterogeneous, accelerator-oriented parallelism is exposed without sufficient abstraction to programmers and compiler writers. As a result, achieving high performance often requires that programs include detailed, platform-specific tailoring, particularly regarding the staging of data as it moves between memory and compute elements, and from one compute element to another. This platform-specific tailoring limits the portability of such programs; when a new chip implementation is released, extensive software reworks are often required to reclaim that high performance. Overall, the result is that heterogeneous parallelism is reducing the performance portability of application software. The DeSCPar research attacks this problem and represents important research in improving programmability. Developed tools will be distributed as free software, including a DeSCPar simulator and design tools. In addition, the project includes a broad set of activities around improving the diversity of the computing workforce.The DeSCPar approach uses Decoupled Supply-Compute Parallelism to achieve portable performance on highly parallel highly-heterogeneous systems. Inspired by Decoupled Access-Execute approaches, DeSCPar likewise decouples value computations from the memory accesses and address computations that "feed" them. By using automated slicing techniques to split code into a data supply portion and a computation portion, high-performance memory optimizations can be achieved while retaining high-level application portability. In DeSCPar, value computation operations are targeted to run on a CompD which may be a hardware accelerator, a specifically-optimized CPU, or a general-purpose CPU. Likewise, memory supply code is aimed at a SuppD, which can be specifically optimized for its task. By employing varied combinations of SuppD and CompD units, richly heterogeneous systems can be built, and software can be automatically mapped onto them. This project: (i) proposes and prototypes automated compiler techniques (based on LLVM) for slicing and optimizing DeSCPar code; and (ii) proposes and evaluates hardware design optimizations based on the DeSCPar organizational structure.