SaTC: TTP: Medium: Collaborative: RESULTS: Reverse Engineering Solutions on Ubiquitous Logic for Trustworthiness and Security

SaTC：TTP：媒介：协作：结果：针对可信性和安全性的普适逻辑的逆向工程解决方案

• 批准号: 1704470
• 负责人: Yier Jin
• 金额: $ 45.22万
• 依托单位: The University of Central Florida Board of Trustees
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-08-01 至 2017-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1704470&HistoricalAwards=false
• 关键词: SaTC; TTP; Medium; Collaborative; RESULTS

Due to the globalization of the integrated circuit (IC) supply chain, the reduction of manufacturing costs and the need for shorter time to market, commercial-off-the-shelf ICs are now prevalent in modern electronic systems. However, the wide usage of such components breeds major security and trust concerns. Validating the security and trustworthiness of these components is extremely challenging since the end user does not have access to the design details. Furthermore, the cost to patch hardware level design flaws and/or hardware Trojans always costs more than patching eventual software vulnerabilities.This project develops an automated trustworthiness and security analysis framework to help end-users address their concerns by reconstructing the behavioral description of commercial-off-the-shelf ICs and analyzing such description for functionality identification and detection of design flaws and/or potentially inserted hardware Trojans and backdoors. This tool suite offers an all-in-one technology to allow engineers to quickly go from physical circuit structure/netlists to behavior/specification and validate the security and trustworthiness of any digital ICs, through data-path and state register identification, state transition graph construction and decomposition, data flow recovery, high-level behavioral design reconstruction, and whitelist- and blacklist-based functionality determination and hardware Trojan/backdoor detection. As a Transition to Practice (TTP) project, the research team is also closely collaborating with an industrial partner in developing, integrating, and validating the tool suite, so that a holistic and practice-oriented hardware security tool suite is provided for protecting the IC supply chain.

由于集成电路（IC）供应链的全球化、制造成本的降低以及对更短的上市时间的需要，商业现成IC现在在现代电子系统中流行。然而，这些组件的广泛使用滋生了重大的安全和信任问题。验证这些组件的安全性和可靠性极具挑战性，因为最终用户无法访问设计细节。此外，委员会认为，修补硬件设计缺陷和/或硬件木马的成本总是高于修补最终软件漏洞的成本。本项目开发了一个自动化的可信度和安全分析框架，通过重建商用现成集成电路的行为描述并分析这些描述以识别功能和检测设计缺陷和/或硬件木马，帮助最终用户解决他们的问题。或可能插入的硬件木马和后门程序。该工具套件提供了一种一体化技术，允许工程师快速从物理电路结构/网表到行为/规范，并通过数据路径和状态寄存器识别、状态转换图构建和分解、数据流恢复、高级行为设计重构、以及基于白名单和黑名单的功能确定和硬件木马/后门检测。作为一个过渡到实践（TTP）项目，研究团队还与工业合作伙伴密切合作，开发，集成和验证工具套件，以便为保护IC供应链提供一个全面和面向实践的硬件安全工具套件。