SaTC: TTP: Medium: Hardware Intellectual Property Protection through Hybrid ASIC/TRAP Integrated Circuit Design

SaTC：TTP：中：通过混合 ASIC/TRAP 集成电路设计保护硬件知识产权

• 批准号: 2155208
• 负责人: Yiorgos Makris
• 金额: $ 90万
• 依托单位: University of Texas at Dallas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-08-15 至 2026-07-31
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2155208&HistoricalAwards=false
• 关键词: SaTC; TTP; Medium; Hardware; Intellectual

As the semiconductor industry transitioned from an in-house fabrication model to a third-party foundry model, it provided widespread access to cutting edge technology at affordable cost and accelerated development of advanced electronic circuits. At the same time, it introduced new concerns regarding protection of the intellectual property of these electronic circuits, whose blueprints must now be shared with globally distributed and potentially untrusted entities involved in the contemporary electronics supply chain. To address these concerns, this project is developing a methodology which enables redaction of proprietary or sensitive portions of an electronic circuit prior to fabrication and reinstatement upon receipt of the final product, thereby protecting the critical intellectual property from theft and/or malicious modification. By focusing on transitioning this technology to practice in collaboration with other academic institutions, industrial partners and federal laboratories, this project addresses the need for high technology-readiness level solutions as well as workforce development. Considering the pervasive development of electronics in every facet of modern life, including critical infrastructure, the objective of this project aligns with NSF's mission "to secure the national defense" and "to advance prosperity".At a technical level, this project builds upon a novel Transistor-Level Programmable (TRAP) fabric which challenges conventional practices in reconfigurable computing by pushing granularity of post-fabrication programmability down to the transistor-level. Thereby, TRAP achieves significant reduction in area, performance and power consumption overhead over conventional Look-Up Table (LUT) based solutions, while at the same time presenting harder obstacles for brute-force or intelligent search-based reverse engineering attacks to overcome. To transition this technology to practice, this project is developing an ecosystem of design tools, training material and proof-of-concept silicon fabrication opportunities, to enable the use of untrusted facilities for manufacturing trusted electronic components while preventing unauthorized entities from being able to understand, use or copy sensitive hardware Intellectual Property.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着半导体行业从内部制造模式过渡到第三方代工模式，它以可承受的成本提供了广泛的尖端技术，并加速了先进电子电路的开发。与此同时，它带来了对这些电子电路知识产权保护的新关切，这些电路的蓝图现在必须与参与当代电子供应链的全球分布和可能不受信任的实体共享。为了解决这些问题，该项目正在开发一种方法，能够在制造之前编辑电子电路的专有或敏感部分，并在收到最终产品后进行修复，从而保护关键知识产权免遭盗窃和/或恶意修改。通过与其他学术机构、工业合作伙伴和联邦实验室合作，专注于将这项技术转化为实践，该项目解决了对高技术就绪水平解决方案和劳动力发展的需求。考虑到电子产品在现代生活的各个方面的普遍发展，包括关键基础设施，该项目的目标与NSF的使命“确保国防”和“促进繁荣”相一致。这个项目建立在一个新的晶体管级可编程（TRAP）结构的基础上，该结构通过推动后处理的粒度来挑战可重构计算中的传统实践，制造可编程性下降到晶体管级。因此，与传统的基于查找表（LUT）的解决方案相比，TRAP实现了面积、性能和功耗开销的显著减少，同时为基于蛮力或智能搜索的逆向工程攻击提出了更难克服的障碍。为了将这项技术转化为实践，该项目正在开发一个由设计工具、培训材料和概念验证硅制造机会组成的生态系统，以便能够使用不可信的设施来制造可信的电子元件，同时防止未经授权的实体能够理解，该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准。