Detection and adaptive prioritization of semi-static data streams and traffic patterns in Network-on-Chips

片上网络中半静态数据流和流量模式的检测和自适应优先级排序

• 批准号: 232927154
• 负责人: Professor Dr.-Ing. Thilo Pionteck
• 金额: --
• 依托单位: Institut für Technische Informatik (ITI)
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2013
• 资助国家: 德国
• 起止时间: 2012-12-31 至 2016-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/232927154?language=en
• 关键词: Detection; adaptive; prioritization; semi; static

Aim of this project is the design and implementation of a traffic adaptive network-on-chip for communication latency reduction in complex manycore systems. Temporally constant communication patterns between functional units should be detected online and the corresponding data streams should be transferred without any delay by bypassing the complete router pipeline. Such temporally constant patterns exist for the duration of an application in multifunctional systems as well as temporally in manycore processor systems with distributed caches. Prioritization of suitable data streams will be applied to individual semi-static data streams between two functional units, as well as to repeating patterns of semi-static data streams. Traffic pattern detection is done locally by each router and only accounts the local routing decisions for all data streams of one router input. This allows local aggregation of several individual data streams with different destination addresses and virtual channel identifiers. If several consecutive routers prioritize the same aggregate, a direct point-to-point connection is set up. Depending on the actual traffic patterns this results in a combination of a packet-oriented and a circuit switched network-on-chip.The frequency of occurrence, duration and pattern of semi-static data streams do not only depend on the communication characteristics between functional blocks and their location, but also on the routing algorithm used. Therefore the effect of different deterministic and adaptive routing algorithms on these parameters needs to be evaluated. It is also intended to use adaptive routing algorithms to support the formation of aggregates of semi-static data streams. Adaptive and fault-tolerant routing algorithms will also be used to limit the effects of blocked networks links for non-prioritized data streams due to their exclusive use for semi-static data streams. Non-prioritized data streams need to be rerouted in such a way that prioritized connections can be sustained as long as possible. The network-on-chip architecture is dedicated for the use in ASIC designs as well as in partially reconfigurable FPGA designs. Performance, energy consumption and hardware requirements will be evaluated for both design alternatives. At the end of the project, the effectiveness of the network-on-chip architecture will be demonstrated by means of an FPGA-based test system.

本项目的目的是设计和实现一种流量自适应的片上网络，以减少复杂多核系统中的通信延迟。应在线检测功能单元之间的临时恒定通信模式，并应通过绕过完整的路由器管道无任何延迟地传输相应的数据流。在多功能系统中以及在具有分布式高速缓存的多核处理器系统中，这种时间上恒定的模式在应用程序的持续时间内存在。适当数据流的优先顺序将应用于两个功能单元之间的单个半静态数据流，以及半静态数据流的重复模式。流量模式检测由每个路由器在本地完成，并且只考虑一个路由器输入的所有数据流的本地路由决策。这允许具有不同目的地地址和虚拟通道标识符的几个单独数据流的本地聚集。如果多个连续的路由器优先处理相同的聚合，则会建立直接的点对点连接。半静态数据流的出现频率、持续时间和模式不仅取决于功能块之间的通信特性及其位置，还取决于所使用的路由算法。因此，需要评估不同的确定性和自适应路由算法对这些参数的影响。它还打算使用自适应路由算法来支持形成半静态数据流的聚集。自适应和容错路由算法还将用于限制阻塞的网络链路对非优先级数据流的影响，因为它们专用于半静态数据流。需要以这样一种方式重新路由未区分优先级的数据流，以使区分优先级的连接能够尽可能长时间地保持。片上网络架构专用于ASIC设计以及部分可重新配置的FPGA设计。将对两种设计方案的性能、能耗和硬件要求进行评估。在项目结束时，将通过一个基于现场可编程门阵列的测试系统来验证片上网络架构的有效性。

项目成果

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs

• DOI: 10.1016/j.micpro.2016.09.011
• 发表时间: 2017-02
• 期刊: Microprocess. Microsystems
• 作者: J. Joseph;Christopher Blochwitz;A. Ortiz;Thilo Pionteck

Adaptive allocation of default router paths in Network-on-Chips for latency reduction

• DOI: 10.1109/hpcsim.2016.7568328
• 发表时间: 2016-07
• 期刊: 2016 International Conference on High Performance Computing & Simulation (HPCS)
• 作者: J. Joseph;Christopher Blochwitz;Thilo Pionteck

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling

周期精确的片上网络模拟器，支持抽象任务图建模

• DOI: 10.1109/issoc.2014.6972440
• 发表时间: 2014
• 期刊: 2014 International Symposium on System-on-Chip (SoC)
• 作者: J. M. Joseph;T. Pionteck
• 通讯作者: T. Pionteck

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip

用于非对称 3D 片上网络设计空间探索的仿真环境

• DOI: 10.1109/recosoc.2016.7533908
• 发表时间: 2016
• 期刊: 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
• 作者: J. M. Joseph;S. Wrieden;C. Blochwitz;A. García-Oritz;T. Pionteck
• 通讯作者: T. Pionteck