SaTC: CORE: Medium: Collaborative: Countermeasures Against Side-Channels Attacks Targeting Hardware and Embedded System Implementations of Post-Quantum Cryptographic Algorithms
SaTC: CORE: Medium: Collaborative: Countermeasures Against Side-Channels Attacks Targeting Hardware and Embedded System Implementations of Post-Quantum Cryptographic Algorithms
批准号:
1801488
负责人:
Mehran Mozaffari Kermani
金额:
$30.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2018
资助国家:
美国
项目状态:
已结题
起止时间:
2018-10-01 至 2024-09-30
中文摘要
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英文摘要
Quantum computers are believed to have a potential to perform specialized calculations beyond the reach of any supercomputer in existence today, threatening today's major public-key cryptography standards. Post-Quantum Cryptography (PQC) is devoted to the design and analysis of cryptographic algorithms that are resistant against any known attacks using quantum computers, but by themselves can be implemented using classical computing platforms, based on current semiconductor technologies. This project aims to develop effective methods of protecting the implementations of emerging PQC schemes against powerful side-channel attacks based on exploiting power consumption of cryptographic devices and/or intentional transient faults affecting their operation.The algorithms to be investigated represent several major PQC families and three major categories of public-key cryptography applications: encryption, digital signature, and key encapsulation mechanism. The goal of the project is to determine the cost of effective countermeasures against power and fault attacks in terms of the commonly accepted software and hardware performance metrics. The research thrusts will (i) investigate the effects of countermeasures against fault attacks on resiliency to power attacks, and (ii) propose solutions to achieve combined fault and power analysis resiliency. The project will involve several significant extensions to preliminarily-developed experimental platform: Flexible Open-source workBench fOr Side-channel analysis (FOBOS).Power and fault attacks are real threats to practical implementation of PQC and may significantly thwart the successful transition to new standards. This project will investigate systematic, long-term study of countermeasures against these attacks, which may make transition to PQC more secure, benefiting Internet users worldwide. The outreach activities will include motivational lectures at high schools, promoting and supervising undergraduate research, and organizing a series of international competitions for graduate students. The knowledge and experience gained will be integrated into several course modules, developed jointly by all investigators and shared on-line.It is expected that multiple algorithms, computer-aided design tools, software programs, and hardware designs will be developed throughout the project period. Project deliverables will be made available to researchers and educators in the non-profit sector, such as universities, research institutions, and government laboratories. To make it easy to maintain, disseminate, and distribute code and data from this project, a single server will be dedicated to keeping all the draft and final copies of the deliverables. This server will be maintained through the project period and additional five years beyond. The project website will be continuously available at http://www.pqcSCA.com.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(12)
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Error Detection Architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE in ${\frac {\mathbb {Z}/p \mathbb {Z}[x]}{x^{n}+1}}$ Benchmarked on ASIC
${frac {mathbb {Z}/p mathbb {Z}[x]}{x^{n} 1}}$ 中环多项式乘法和环-LWE 模约化的错误检测架构在 ASIC 上进行基准测试
DOI:
10.1109/tr.2020.2991671
发表时间:
2020
期刊:
IEEE Transactions on Reliability
影响因子:
5.9
作者:
[Sarker, Ausmita, Kermani, Mehran Mozaffari, Azarderakhsh, Reza]
通讯作者:
Azarderakhsh, Reza
DOI:
10.1109/tvlsi.2020.3031170
发表时间:
2021-01-01
期刊:
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
影响因子:
2.8
作者:
[Canto, Alvaro Cintas, Mozaffari-Kermani, Mehran, Azarderakhsh, Reza]
通讯作者:
Azarderakhsh, Reza
Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures
安全密码体系结构中数论变换错误检测的硬件结构
DOI:
10.1109/tvlsi.2018.2881097
发表时间:
2019
期刊:
IEEE Transactions on Very Large Scale Integration (VLSI
影响因子:
--
作者:
[Sarker, Ausmita, Mozaffari-Kermani, Mehran, Azarderakhsh, Reza]
通讯作者:
Azarderakhsh, Reza
DOI:
10.1109/tr.2022.3216014
发表时间:
2023-06
期刊:
IEEE Transactions on Reliability
影响因子:
5.9
作者:
[Alvaro Cintas-Canto;Mehran Mozaffari Kermani;R. Azarderakhsh]
通讯作者:
Alvaro Cintas-Canto;Mehran Mozaffari Kermani;R. Azarderakhsh
Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA
FPGA上基于代码的后量子密码系统密钥生成器的可靠构建
DOI:
10.1145/3544921
发表时间:
2023
期刊:
ACM Journal on Emerging Technologies in Computing Systems
影响因子:
2.2
作者:
[Canto, Alvaro Cintas, Kermani, Mehran Mozaffari, Azarderakhsh, Reza]
通讯作者:
Azarderakhsh, Reza
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