SBIR Phase I: Energy Efficient Neural Network Accelerator Featuring a Logic Compatible Non-Volatile Synapse Array

SBIR 第一阶段：具有逻辑兼容非易失性突触阵列的节能神经网络加速器

• 批准号: 1843483
• 负责人: Seung-Hwan Song
• 金额: $ 22.49万
• 依托单位: Anaflash Inc.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-02-01 至 2019-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1843483&HistoricalAwards=false
• 关键词: SBIR; Phase; Energy; Efficient; Neural

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to accelerate the adoption of AI features in Internet of Things and mobile devices. The proposed multi-bit non-volatile memory (NVM) based Deep Neural Networks (DNN) IP is based on the standard CMOS logic processes. Existing solution for the DNN hardware typically requires off-chip access to retrieve neural network parameters from external memories, incurring additional communication latency and power consumption. Additionally, when critical neural network parameters are transmitted off-chip, security or privacy concern may arise, which is unacceptable especially for the applications such as personalized AI devices. Alternative approach integrating the DNN engine in a special NVM process requires as much as 10 additional masks beyond the conventional logic CMOS process which is not cost-effective for medium density DNN engine in cost-sensitive edge devices. With this proposed IP, any existing or new system on chip requiring persistent AI functionality can be built quickly and cost effectively.This Small Business Innovation Research (SBIR) Phase I project seeks to develop a cost-effective non-volatile neural network accelerator IP for edge devices. To solve the security, latency, power consumption, and cost issues associated with the traditional approaches, a single-poly based low cost, non-volatile, multi-bit eFlash cell is proposed. Multi-bit cell operation however presents significant challenges due to inherent reduction in signal-to-noise ratio. Key technical hurdles include solving disturbances of unselected cells, improving sensing margin, and overcoming reliability issues associated with high voltage operation in readout circuits as well as developing robust neural network cell arrays. To address these challenges, several new ideas related to multi-bit cell, high-voltage circuits, and cell programming methods have been proposed. Once verified successfully in this project, the multi-bit cell IP can then be integrated as logic compatible non-volatile memory to store neural network parameters on-chip, or as logic compatible non-volatile neural network IP to execute entire neural network operation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

这项小企业创新研究（SBIR）第一阶段项目的更广泛影响/商业潜力是加速人工智能功能在物联网和移动设备中的应用。提出的基于多位非易失性存储器（NVM）的深度神经网络（DNN） IP基于标准CMOS逻辑流程。现有的DNN硬件解决方案通常需要片外访问从外部存储器检索神经网络参数，从而导致额外的通信延迟和功耗。此外，当关键的神经网络参数在片外传输时，可能会出现安全或隐私问题，这对于个性化人工智能设备等应用来说是不可接受的。在特殊的NVM工艺中集成DNN引擎的另一种方法需要比传统的逻辑CMOS工艺多10个额外的掩模，这对于成本敏感边缘设备中的中密度DNN引擎来说是不划算的。有了这个建议的IP，任何现有的或新的芯片上的系统需要持久的人工智能功能可以快速和经济有效地构建。这项小企业创新研究（SBIR）第一阶段项目旨在为边缘设备开发一种具有成本效益的非易失性神经网络加速器IP。为了解决与传统方法相关的安全性、延迟、功耗和成本问题，提出了一种基于单poly的低成本、非易失性、多比特eFlash单元。然而，由于固有的信噪比降低，多比特单元操作带来了重大挑战。关键的技术障碍包括解决非选择单元的干扰，提高传感裕度，克服与读出电路中高压操作相关的可靠性问题，以及开发鲁棒的神经网络单元阵列。为了应对这些挑战，人们提出了一些与多比特单元、高压电路和单元编程方法相关的新想法。一旦在该项目中验证成功，那么多比特单元IP就可以集成为逻辑兼容的非易失性存储器，以存储芯片上的神经网络参数，或者作为逻辑兼容的非易失性神经网络IP来执行整个神经网络操作。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。