Optimization of 100 Gb/s Short Range Wireless Transceivers under Processing-Energy Constraints

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Subject of this project is the scientific investigation of novel concepts for wireless short range transceivers operating at carrier frequencies of 60 GHz or 120 GHz and with a bandwidth between 1 and 10 GHz. A particular processing-energy per information bit leads to a power consumption increasing disproportionally high with the data rate. For data rates in the order of 100 Gb/s the power consumed by the transceiver will become a severe issue. Therefore, in this project transceivers will be optimized for maximum throughput especially under constraints on the total consumed energy, i.e. on transmit- and on processing-energy, per information bit and, thus, on the power consumed for a given information bit rate. In order to achieve the objectives, we will study suitable radio-frequency (RF) architectures and transmission schemes jointly with energy-efficient architectures and their implementation in a real cross layer approach. This inevitably requires a power consumption based design space exploration. Major challenges are in the approaches to achieve transmission rates in the order of 100 Gb/s and in an analog/digital partitioning of the signal processing tasks that supports the data rates but stays within acceptable limits for the consumed energy per information bit.The key objectives of this project thus lie in the design of innovative RF, mixed-signal, and digital signal processing architectures to achieve high power efficiency, bandwidth efficiency and implementation efficiency for ultra-high data rates. To achieve the main objectives a number of key problems has to be researched. This includes, in particular, realization of high modulation orders, many-antenna transmission, partitioning into analog and digital signal processing, digitally adjusted/switched analog processing, and energy efficient silicon implementation. For all concepts their impact on the throughput and their contribution to the total energy consumption will be key parameters. Thus, energy/power estimation and budgeting is a further key research topic of this project. After researching system architectures for 60 GHz and power-efficient implementation of the digital signal processing in the first phase, in the second phase critical components will be implemented on silicon and their performance will be compared to the behavior, which was determined by theoretical analysis and by simulation. Further, power-optimized system architectures for the 120 GHz range (and beyond) will be studied and this work will also be used to validate the power consumption based design space exploration method, developed in the first phase.