I-Corps Teams: Seeking Commercialization Potentials of a New Interconnect based Nanoscale Computing Technology for Future Digital Integrated Circuits

I-Corps项目的广泛影响/商业潜力可能是重大的，因为它可以为计算机芯片持续小型化的突破性研究提供商业化途径。对于日常使用的数字电子产品来说，更小、更好的芯片意味着更低的成本、更高的性能和更多的功能。传统的集成电路缩放方式在亚10nm技术节点上遇到了不可逾越的障碍，该技术通过从基础物理组件、计算模型到电路和集成等多个层面的创新，为集成电路的缩放提供了新的方向。此外，该技术承诺更密集、更快、更节能的计算，通过固有的物理能力和设计选择，具有容错和安全硬件的独特能力。该技术与基于知识产权（IP）开发战略的无晶圆厂商业化方法相结合，在快速周转时间内实现市场渗透和增长。该产品将有利于从微处理器生产商到消费电子制造商的广泛客户，对国防实体尤其有吸引力。这个I-corps团队项目将为成功的SBIR/STTR提案提供客户发现、商业模式生成和商业化潜力评估，并最终将实验室研究转化为产品。它将对参与者产生持久的影响。这个I-Corps项目寻求一种新型计算技术的商业化潜力，该技术依赖于相邻纳米级互连（串扰）之间的确定性干扰进行逻辑计算。该方法摆脱了当前依赖于设备切换的计算范式，并放宽了困难的设备缩放要求。串扰结构的可扩展性主要取决于电路方案、集成以及绘制更小的金属纳米线和在它们之间沉积介电体的能力，这可以通过利用现有的EDA和制造方法来完成。所提出的计算方法在功能上是完整的，并为逻辑简化提供了巨大的机会；通过将两个以上的输入耦合到一个输出，并通过改变它们各自的耦合电容，在CMOS中通常需要超过15个晶体管的逻辑实现（例如，加法的进位逻辑）只需要5个晶体管就可以完成。4位加法器的基准测试显示，与16nm的CMOS相比，4位加法器的密度优势超过5倍。串扰技术的另一个显著特征是运行时可重构性，它允许在同一电路中嵌入不同的功能，这可以改变容错性（即，如果CPU的一部分损坏，功能部分可以配置为同时执行这两项任务）和网络安全。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this I-Corps project can be significant as it can provide pathways for commercialization of a breakthrough research for continuous miniaturization of computer chips. For the digital electronics in everyday use, smaller and better chips imply lesser cost, higher performance, and more features. As traditional way of IC scaling reaches unsurmountable barriers at sub-10nm technology nodes, the proposed technology provides new directions for scaling through innovations in several layers from fundamental physical components, computing model, to circuits and integration. In addition, the technology promises denser, faster and more power efficient computing with unique capabilities for fault-tolerant and secure hardware through inherent physical capabilities and design choices. The technology, coupled with Intellectual Property (IP) development strategy based fabless commercialization approach is proposed for market penetration and growth at a fast turn-around time. The product will be beneficial for a wide range of customers from microprocessor producers to consumer electronics manufacturers and be particularly attractive for defense entities. This I-corps teams project will allow customer discovery, business model generation and evaluation of commercialization potentials for successful SBIR/STTR proposals, and can ultimately lead to the transition of lab research to product. It will have a lasting impact on the participants. This I-Corps project seeks commercialization potential of a novel computing technology that relies on deterministic interference between adjacent nanoscale interconnects (Crosstalk) for logic computing. The proposed approach departs from current device switching dependent computing paradigm and relaxes difficult device scaling requirements. The scalability in Crosstalk fabric is determined primarily by circuit scheme, integration and the ability to pattern smaller metal nano-lines and deposit dielectrics in between them, which can be done by utilizing existing EDA and manufacturing methods. The proposed computing approach is functionally complete, and provides huge opportunities for logic reduction; by having more than 2 inputs couple to a single output and by varying their respective coupling capacitances, a logic implementation (e.g., Carry logic for Addition) that would typically require more than 15 transistors in CMOS, can be done by just 5 transistors. The benchmarking of a 4-bit adder showed over 5x density benefits vs. CMOS at 16nm. Another distinct feature of Crosstalk technology is the run-time reconfigurability that allows different functionalities to be embedded in the same circuit, which can be transformative for fault tolerance (i.e., if a portion of CPU is damaged, the functioning portion can be configured to do both tasks), and cybersecurity.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.