I-Corps Teams: Seeking Commercialization Potentials of a New Interconnect based Nanoscale Computing Technology for Future Digital Integrated Circuits

I-Corps 团队：为未来数字集成电路寻求基于新型互连的纳米级计算技术的商业化潜力

• 批准号: 1903575
• 负责人: Mostafizur Rahman
• 金额: $ 5万
• 依托单位: University of Missouri-Kansas City
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-12-01 至 2020-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1903575&HistoricalAwards=false
• 关键词: Corps; Teams; Seeking; Commercialization; Potentials

The broader impact/commercial potential of this I-Corps project can be significant as it can provide pathways for commercialization of a breakthrough research for continuous miniaturization of computer chips. For the digital electronics in everyday use, smaller and better chips imply lesser cost, higher performance, and more features. As traditional way of IC scaling reaches unsurmountable barriers at sub-10nm technology nodes, the proposed technology provides new directions for scaling through innovations in several layers from fundamental physical components, computing model, to circuits and integration. In addition, the technology promises denser, faster and more power efficient computing with unique capabilities for fault-tolerant and secure hardware through inherent physical capabilities and design choices. The technology, coupled with Intellectual Property (IP) development strategy based fabless commercialization approach is proposed for market penetration and growth at a fast turn-around time. The product will be beneficial for a wide range of customers from microprocessor producers to consumer electronics manufacturers and be particularly attractive for defense entities. This I-corps teams project will allow customer discovery, business model generation and evaluation of commercialization potentials for successful SBIR/STTR proposals, and can ultimately lead to the transition of lab research to product. It will have a lasting impact on the participants. This I-Corps project seeks commercialization potential of a novel computing technology that relies on deterministic interference between adjacent nanoscale interconnects (Crosstalk) for logic computing. The proposed approach departs from current device switching dependent computing paradigm and relaxes difficult device scaling requirements. The scalability in Crosstalk fabric is determined primarily by circuit scheme, integration and the ability to pattern smaller metal nano-lines and deposit dielectrics in between them, which can be done by utilizing existing EDA and manufacturing methods. The proposed computing approach is functionally complete, and provides huge opportunities for logic reduction; by having more than 2 inputs couple to a single output and by varying their respective coupling capacitances, a logic implementation (e.g., Carry logic for Addition) that would typically require more than 15 transistors in CMOS, can be done by just 5 transistors. The benchmarking of a 4-bit adder showed over 5x density benefits vs. CMOS at 16nm. Another distinct feature of Crosstalk technology is the run-time reconfigurability that allows different functionalities to be embedded in the same circuit, which can be transformative for fault tolerance (i.e., if a portion of CPU is damaged, the functioning portion can be configured to do both tasks), and cybersecurity.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

这个I-Corps项目的更广泛的影响/商业潜力可能是重要的，因为它可以为计算机芯片持续小型化的突破性研究的商业化提供途径。对于日常使用的数字电子产品来说，更小、更好的芯片意味着更低的成本、更高的性能和更多的功能。由于传统的IC缩放方式在10 nm以下的技术节点上达到了无法逾越的障碍，因此所提出的技术通过从基本物理组件、计算模型到电路和集成的几个层的创新为缩放提供了新的方向。此外，该技术通过固有的物理能力和设计选择，提供了更密集、更快速、更节能的计算能力，并具有独特的容错和安全硬件能力。该技术，再加上知识产权（IP）的发展战略为基础的无晶圆厂商业化的方法，提出了市场渗透和增长在一个快速的周转时间。 该产品将有利于从微处理器生产商到消费电子制造商的广泛客户，对国防实体特别有吸引力。这个I-Corps团队项目将允许客户发现，商业模式生成和成功SBIR/STTR提案的商业化潜力评估，并最终导致实验室研究向产品的过渡。它将对参与者产生持久的影响。 这个I-Corps项目寻求一种新型计算技术的商业化潜力，该技术依赖于相邻纳米级互连之间的确定性干扰（串扰）进行逻辑计算。所提出的方法从当前的设备切换依赖的计算范例和放松困难的设备缩放要求。串扰结构中的可扩展性主要由电路方案、集成和图案化较小金属纳米线并在它们之间存款的能力来确定，这可以通过利用现有的EDA和制造方法来完成。所提出的计算方法在功能上是完整的，并且为逻辑简化提供了巨大的机会;通过使多于2个输入耦合到单个输出并且通过改变它们各自的耦合电容，逻辑实现（例如，加法的进位逻辑）通常需要15个以上的CMOS晶体管，但只需5个晶体管就可以完成。4位加法器的基准测试显示，与16 nm CMOS相比，其密度优势超过5倍。串扰技术的另一个明显特征是运行时可重构性，其允许不同的功能嵌入在同一电路中，这对于容错来说可以是变革性的（即，该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。