FoMR: Speculative Super-optimization: Boosting Performance via Speculation-Driven Dynamic Binary Optimization

FoMR：推测性超级优化：通过推测驱动的动态二进制优化提高性能

• 批准号: 1912608
• 负责人: Ashish Venkat
• 金额: $ 20万
• 依托单位: University of Virginia Main Campus
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-10-01 至 2023-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1912608&HistoricalAwards=false
• 关键词: FoMR; Speculative; Super; optimization; Boosting

Modern processors are characterized by increasing 'core' counts on a single multi-core processor, where a 'core' is a computing unit, allowing each core to operate in parallel to, and independently of, other cores on the processor. Yet, a substantial chunk of software applications is inherently sequential. Although modern compilers feature sophisticated optimizations, significant waste of computational resources across these multiple-cores still occurs due to computational patterns that are unpredictable at compile-time. This project explores techniques to deploy aggressive speculative dynamic optimizations within the micro-processor, enabling continuous optimization of inherently sequential code. This work addresses a pressing need for systems that can aggressively and yet seamlessly super-optimize machine code, adapting to the dynamic execution environment, and thereby speed up execution of applications on computers. This research will also foster existing efforts and initiatives of the investigators to build a pipeline of students from diverse backgrounds.This project explores dynamic binary optimization techniques at the processor level to speculatively generate and execute a super-optimized instruction stream, by leveraging established speculative processor features such as branch prediction, value prediction, and loop stream detection. This project introduces two distinct flavors of speculative super-optimization: (a) a hardware implementation that leverages dynamically predicted program state to perform simple, yet powerful peephole optimizations on short instruction sequences, and (b) a firmware implementation that leverages a microcode-based dynamic re-compiler running as a helper thread to perform more sophisticated optimizations. Owing to the plethora of speculative processor features and compiler/runtime/hardware optimizations to choose from, this project explores a rich sample space of speculative super-optimization strategies, along with extensive profitability analysis to dynamically identify appropriate targets for super-optimization.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

现代处理器的特征是增加了单个多核处理器上的“核心”计数，其中“核心”是一个计算单元，允许每个核心与处理器上的其他内核并行操作。但是，大量软件应用程序本质上是顺序的。 尽管现代编译器具有复杂的优化，但由于计算模式在编译时不可预测，这些多核的计算资源仍然存在大量浪费。 该项目探讨了在微观处理器内部署积极投机动态优化的技术，从而使固有顺序代码的连续优化能够连续优化。 这项工作解决了对可以积极而又无缝超级优化的机器代码，适应动态执行环境的系统的紧迫需求，从而加快了计算机上的应用程序的执行。 这项研究还将促进研究人员的现有努力和计划，以建立来自不同背景的学生的管道。本项目通过利用已确定的投机性处理器（例如分支预测，价值预测和循环流探测器）来探索处理器级别的动态二进制优化技术，以推测生成和执行超级优化的指令流。 该项目引入了投机性超级优化的两种不同的口味：（a）一种硬件实现，它利用动态预测的程序状态在短说明序列上执行简单但功能强大的窥视孔优化，（b）固件实现，利用基于微型的DynamiC Recompiler Remanter运行的Helper Remanter作为Helper helper theme and Helper the Helper the Helper temal inst osal ins ost Older of Selper temal inster of Compopsifections更加复杂。 由于要选择的大量投机处理器功能和编译器/运行时/硬件优化，该项目将探讨投机性超级优化策略的丰富样本空间，以及广泛的盈利能力分析，以动态地确定适当的目标，以识别超级优先级的奖励，这些奖项反映了NSF的法规及其依据，并在广泛的范围内得到了依据，并构成了构成的构成，这是构成的支持。 标准。

项目成果

I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches

我看到死微操作：通过 Intel/AMD 微操作缓存泄露秘密

• DOI: 10.1109/isca52012.2021.00036
• 发表时间: 2021
• 期刊: 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA
• 作者: Ren, Xida;Moody, Logan;Taram, Mohammadkazem;Jordan, Matthew;Tullsen, Dean M.;Venkat, Ashish
• 通讯作者: Venkat, Ashish

Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations

推测性代码压缩：通过推测性微代码转换消除死代码

• DOI: 10.1109/micro56248.2022.00024
• 发表时间: 2022
• 期刊: 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO
• 作者: Moody, Logan;Qi, Wei;Sharifi, Abdolrasoul;Berry, Layne;Rudek, Joey;Gaur, Jayesh;Parkhurst, Jeff;Subramoney, Sreenivas;Skadron, Kevin;Venkat, Ashish
• 通讯作者: Venkat, Ashish

CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities

• DOI: 10.1109/isca45697.2020.00068
• 发表时间: 2020-05
• 期刊: 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
• 作者: Rasool Sharifi;A. Venkat

Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching

• DOI: 10.1109/isca52012.2021.00028
• 发表时间: 2021-06
• 期刊: 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)
• 作者: Lingxi Wu;Rasool Sharifi;Marzieh Lenjani;K. Skadron;A. Venkat

SecSMT: Securing SMT Processors against Contention-Based Covert Channels

• 发表时间: 2022
• 作者: Mohammadkazem Taram;Xida Ren;A. Venkat;D. Tullsen