Collaborative Research: FoMR: Enabling High Instructions-per-Cycle (IPC) Counts in Future Multi-NUMA (Non Uniform Memory Access) Systems

新兴的存储器技术，如三维芯片堆叠式动态随机存取存储器(3D-DRAM)和非易失性随机存取存储器(NVRAM)，在实现计算机处理器的高性能方面带来了很有希望的机会。具有混合存储器技术的计算机服务器引入了新的多维非均匀存储器访问(MULTI-NUMA)方法，其中计算机存储器层次结构根据存储器的类型和其在系统中的驻留位置而具有广泛不同的性能和效率特性。尽管多NUMA系统有很好的好处，但由于它们引入的异构性水平，多NUMA系统带来了巨大的体系结构设计挑战。从访问延迟、带宽和访问粒度到可靠性和功能性的多维异构性使得存储器层次结构的性能和访问行为难以预测和操纵。解决这些问题可能会影响构建高效多NUMA系统的体系结构设计，还会催生新的应用程序，这些应用程序可以处理比目前可能的更大数量的异类数据。该项目旨在提高未来采用混合内存技术的服务器系统的性能。为了实现这一目标，该项目包括三个阶段。第一阶段旨在通过包含多NUMA方案，重新调查存储器层次结构体系结构设计的基本性能模型、假设和度量，包括存储器系统性能、可靠性和可扩展性。在多NUMA感知体系结构设计策略的指导下，第二阶段将重点重新考虑内存层次体系结构组件的设计，这些组件对应用程序的每周期指令数(IPC)性能至关重要。最后，第三阶段旨在确保在多插槽和基于内存结构的多NUMA系统中可扩展的IPC性能。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

Emerging memory technologies, such as three-dimensional die-stacked dynamic random access memory (3D-DRAM) and non-volatile random-access memory (NVRAM), introduce promising opportunities in achieving high performance for computer processors. Computer servers with mixed memory technologies introduce a new multi-dimensional non-uniform memory access (“multi-NUMA”) method, where the computer memory hierarchy has widely varying performance and efficiency characteristics depending on the type of memory and where it resides in the system. Despite the promising benefits, multi-NUMA systems impose significant architecture design challenges due to the level of heterogeneity they introduce. The multi-dimensional heterogeneity, which ranges from access latency, bandwidth, and access granularity to reliability and functionality, makes memory hierarchy performance and access behavior difficult to predict and manipulate. Addressing these issues can influence the architecture design for building efficient multi-NUMA systems and also spawn new applications that can deal with larger volumes of heterogeneous data than what is possible at present.This project aims to improve the performance of future server systems that incorporate mixed memory technologies. To achieve the objective, this project consists of three phases. The first phase seeks to reinvestigate the basic performance models, assumptions, and metrics of memory hierarchy architecture design, across memory system performance, reliability, and scalability, by encompassing the multi-NUMA scenario. Guided by the multi-NUMA-aware architecture design strategies, the second phase will focus on reconsidering the design of memory hierarchy architecture components that are critical to the application’s instructions-per-cycle (IPC) performance. Finally, the third phase seeks to ensure scalable IPC performance in both multi-socket and memory-fabric-based multi-NUMA systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.