Collaborative Research: FoMR: Enabling High Instructions-per-Cycle (IPC) Counts in Future Multi-NUMA (Non Uniform Memory Access) Systems

合作研究：FoMR：在未来的多 NUMA（非均匀内存访问）系统中实现高每周期指令 (IPC) 计数

• 批准号: 2011213
• 负责人: Joseph Izraelevitz
• 金额: $ 9.5万
• 依托单位: University of Colorado at Boulder
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-07-15 至 2023-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2011213&HistoricalAwards=false
• 关键词: Collaborative; Research; FoMR; Enabling; Instructions

Emerging memory technologies, such as three-dimensional die-stacked dynamic random access memory (3D-DRAM) and non-volatile random-access memory (NVRAM), introduce promising opportunities in achieving high performance for computer processors. Computer servers with mixed memory technologies introduce a new multi-dimensional non-uniform memory access (“multi-NUMA”) method, where the computer memory hierarchy has widely varying performance and efficiency characteristics depending on the type of memory and where it resides in the system. Despite the promising benefits, multi-NUMA systems impose significant architecture design challenges due to the level of heterogeneity they introduce. The multi-dimensional heterogeneity, which ranges from access latency, bandwidth, and access granularity to reliability and functionality, makes memory hierarchy performance and access behavior difficult to predict and manipulate. Addressing these issues can influence the architecture design for building efficient multi-NUMA systems and also spawn new applications that can deal with larger volumes of heterogeneous data than what is possible at present.This project aims to improve the performance of future server systems that incorporate mixed memory technologies. To achieve the objective, this project consists of three phases. The first phase seeks to reinvestigate the basic performance models, assumptions, and metrics of memory hierarchy architecture design, across memory system performance, reliability, and scalability, by encompassing the multi-NUMA scenario. Guided by the multi-NUMA-aware architecture design strategies, the second phase will focus on reconsidering the design of memory hierarchy architecture components that are critical to the application’s instructions-per-cycle (IPC) performance. Finally, the third phase seeks to ensure scalable IPC performance in both multi-socket and memory-fabric-based multi-NUMA systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

新兴的内存技术，例如三维模具堆叠的动态随机访问存储器（3D-DRAM）和非挥发性随机记忆（NVRAM），为实现计算机处理器高性能提供了希望的机会。使用混合内存技术的计算机服务器引入了一种新的多维非均匀内存访问（“多名”）方法，其中计算机存储器层次结构具有较大的性能和效率特征，具体取决于内存的类型及其在系统中的位置。尽管有希望的好处，但由于它们引入的异质性水平，多名系统对架构设计挑战构成了重大的建筑设计挑战。多维异质性的范围从访问延迟，带宽和访问粒度到可靠性和功能，使内存层次结构的性能和访问行为难以预测和操纵。解决这些问题可能会影响建筑有效的多名系统的架构设计，并产生可以处理大量异质数据的新应用程序，而不是目前的可能性。该项目旨在提高结合混合记忆技术的未来服务器系统的性能。为了实现目标，该项目由三个阶段组成。第一阶段旨在通过涵盖多名场景，跨内存系统性能，可靠性和可扩展性来重新分配内存层次结构设计的基本性能模型，假设和指标。在多态感知体系结构设计策略的指导下，第二阶段将重点介绍对记忆层次结构架构组件的设计，这对于应用程序的指令 - 每循环（IPC）性能至关重要。最后，第三阶段旨在确保基于多插座和基于内存的多名数据系统中的可扩展IPC性能。该奖项反映了NSF的法定任务，并通过使用基金会的知识分子和更广泛的影响审查标准来评估NSF的法定任务。

项目成果

Zhuque: Failure is Not an Option, it's an Exception

• 发表时间: 2023
• 作者: G. Hodgkins;Yi Xu;S. Swanson;Joseph Izraelevitz

SubZero: zero-copy IO for persistent main memory file systems

SubZero：持久主内存文件系统的零拷贝 IO

• DOI: 10.1145/3409963.3410489
• 发表时间: 2020
• 期刊: ACM SIGOPS Asia-Pacific Workshop on Systems (APSys
• 作者: Kim, Juno;Soh, Yun Joon;Izraelevitz, Joseph;Zhao, Jishen;Swanson, Steven
• 通讯作者: Swanson, Steven