Collaborative Research: FoMR: Enabling High Instructions-per-Cycle (IPC) Counts in Future Multi-NUMA (Non Uniform Memory Access) Systems

新兴的存储技术，如三维叠片动态随机存取存储器（3D-DRAM）和非易失性随机存取存储器（NVRAM），为实现计算机处理器的高性能提供了有希望的机会。使用混合内存技术的计算机服务器引入了一种新的多维非均匀内存访问（“multi-NUMA”）方法，其中计算机内存层次结构根据内存类型及其在系统中的位置具有广泛不同的性能和效率特征。尽管多numa系统有很大的好处，但由于它们引入的异构程度，它们给架构设计带来了重大挑战。多维异质性（从访问延迟、带宽、访问粒度到可靠性和功能）使得内存层次结构性能和访问行为难以预测和操作。解决这些问题可以影响构建高效多numa系统的体系结构设计，还可以生成新的应用程序，这些应用程序可以处理比目前可能处理的更大量的异构数据。这个项目的目的是提高未来采用混合内存技术的服务器系统的性能。为了实现这一目标，本项目分为三个阶段。第一阶段旨在通过包含多numa场景，重新研究内存系统性能、可靠性和可伸缩性方面的基本性能模型、假设和内存层次体系结构设计指标。在多numa感知架构设计策略的指导下，第二阶段将重点重新考虑内存层次架构组件的设计，这些组件对应用程序的每周期指令（IPC）性能至关重要。最后，第三阶段寻求在多套接字和基于内存结构的多numa系统中确保可扩展的IPC性能。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Emerging memory technologies, such as three-dimensional die-stacked dynamic random access memory (3D-DRAM) and non-volatile random-access memory (NVRAM), introduce promising opportunities in achieving high performance for computer processors. Computer servers with mixed memory technologies introduce a new multi-dimensional non-uniform memory access (“multi-NUMA”) method, where the computer memory hierarchy has widely varying performance and efficiency characteristics depending on the type of memory and where it resides in the system. Despite the promising benefits, multi-NUMA systems impose significant architecture design challenges due to the level of heterogeneity they introduce. The multi-dimensional heterogeneity, which ranges from access latency, bandwidth, and access granularity to reliability and functionality, makes memory hierarchy performance and access behavior difficult to predict and manipulate. Addressing these issues can influence the architecture design for building efficient multi-NUMA systems and also spawn new applications that can deal with larger volumes of heterogeneous data than what is possible at present.This project aims to improve the performance of future server systems that incorporate mixed memory technologies. To achieve the objective, this project consists of three phases. The first phase seeks to reinvestigate the basic performance models, assumptions, and metrics of memory hierarchy architecture design, across memory system performance, reliability, and scalability, by encompassing the multi-NUMA scenario. Guided by the multi-NUMA-aware architecture design strategies, the second phase will focus on reconsidering the design of memory hierarchy architecture components that are critical to the application’s instructions-per-cycle (IPC) performance. Finally, the third phase seeks to ensure scalable IPC performance in both multi-socket and memory-fabric-based multi-NUMA systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.