Scaling and Performance Potential of Bilayer Graphene Field Effect Transistors for Analog Applications

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The focus of this project is on the investigation of performance parameters and the scaling potential of bilayer graphene field effect transistors (GFETs) for RF analog applications. RF transistors, such as targeted here, benefit from a channel material with high carrier mobility and a reasonable band gap. In contrast to single layer graphene, a band gap of a few 100 meV can be opened in bilayer graphene by applying a vertical electric field across the two layers. In this project, we will achieve this by fabricating double gate transistors with two independently controllable gate electrodes. Most likely, Bernal stacking is required to achieve this goal, but there are some indications that random orientations might also work. We intend to grow the required bilayer graphene films by chemical vapor deposition (CVD) on catalytic surfaces like copper foils and copper films on silicon oxide. Initial deposition experiments will be carried out in a CVD furnace, followed by the investigation of plasma enhanced CVD technology to reduce the processing temperatures. The deposited layers will be transferred onto the desired silicon substrates, where they will serve as the channel material for bilayer GFETs. Micro- and nanotechnologies will be used to fabricate the GEFTs, and electron beam lithography will be employed to fabricate devices with a variety of gate lengths down to 20 nm.The RF performance potential of transistors can be assessed to a great extent with DC parameters. We will therefore study in particular the intrinsic transconductance gm, the drain conductance gds and the intrinsic voltage gain AV. Based on the experiments, we will identify optima in the trade off between carrier mobility and band gap. Gate length variations and temperature dependent measurements will enable us to study the effects of gate length scaling on the RF performance and to assess electric transport properties in the ballistic limit.