STTR Phase I: Rebooting Artificial Intelligence Inference with a New Configurable Computing Fabric

这个小型企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力是改善数据利用和实时智能决策。所提出的技术是一种新的可重构计算平台，能够以分布式和并行方式执行各种人工智能（AI）任务，以较低的成本提供最佳性能。最终产品是AI加速器芯片，可以集成在加速卡中，也可以作为协处理器应用于服务器和边缘计算解决方案中，以加速AI任务。对于数据中心和云计算行业来说，一般市场需求尤其迫切，因为这些行业的主要痛点是性能瓶颈和由于定制芯片或依赖图形处理单元而导致的高成本。该技术的核心价值主张是更快的计算速度，运行时可编程性，以及更容易与现有软件集成，以实现流行的机器学习框架的执行。这个小型企业创新研究阶段（SBIR）第一阶段项目围绕一种新颖的计算方法，其中计算和存储元素是并行和分布式的，计算元素之间的互连是灵活的。该项目开发了一种集成电路芯片，可以在运行时重新配置，作为每个运行的人工智能（AI）应用程序的定制专用集成电路，以提供最佳性能。它将克服传统计算技术所面临的内存瓶颈，即数据需要不断地加载到内存和从内存加载。 所提出的技术还解决了不断发展的AI模型和数据集的适应性挑战。拟议的活动包括使用28纳米商业半导体代工工艺进行芯片制造，对新技术的可扩展性进行广泛的基准测试，对数据大小和形状的适应性，以及对软件接口的研究，以执行新芯片中现有机器学习框架开发的代码。原型芯片预计将展示分布式和并行计算能力沿着与动态可重构性。 该基准测试工作预计将揭示至少一个数量级的改进，比更传统的图形处理单元为基础的approaches.This奖项反映了NSF的法定使命，并已被认为是值得的支持，通过评估使用基金会的智力价值和更广泛的影响审查标准。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to improve data harnessing and real-time intelligent decision making. The proposed technology is a new reconfigurable computing platform capable of performing a variety of Artificial Intelligence (AI) tasks in a distributed and parallel manner to deliver the best performance at a lower cost. The end products are AI accelerator chips that can be integrated in Accelerator Cards or as co-processors to be applied in both server and edge computing solutions to accelerate AI tasks. The general market need is particularly acute for data center and cloud computing industries where major pain points are performance bottlenecks and high costs due to custom chips or reliance on graphic processing units. The core value propositions of the proposed technology are faster compute, programmability at run-time, and easier integration with existing software to enable execution of popular machine learning frameworks.This Small Business Innovation Research Phase (SBIR) Phase I project centers around a novel computing approach where computing and memory elements are parallel and distributed, and interconnection between computing elements is flexible. The project develops an integrated circuit chip that can be reconfigured at run-time to behave as a custom application-specific integrated circuit for each running Artificial Intelligence (AI) application to deliver the optimal performance. It will overcome the memory bottleneck that traditional computing technologies face where data needs to be continuously loaded to and from memory. The proposed technology also addresses the adaptivity challenge for evolving AI models and datasets. The proposed activities include a chip fabrication using a 28nm commercial semiconductor foundry process, extensive benchmarking of the new technology for scalability, adaptability to data size and shape, and research on a software interface to execute codes developed by existing machine learning frameworks in the new chip. The prototype chip is expected to demonstrate distributed and parallel computing capabilities along with dynamic reconfigurability. The benchmarking work is anticipated to reveal at least an order of magnitude improvement over more conventional graphics processing unit based approaches.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.