STTR Phase I: Rebooting Artificial Intelligence Inference with a New Configurable Computing Fabric

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The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to improve data harnessing and real-time intelligent decision making. The proposed technology is a new reconfigurable computing platform capable of performing a variety of Artificial Intelligence (AI) tasks in a distributed and parallel manner to deliver the best performance at a lower cost. The end products are AI accelerator chips that can be integrated in Accelerator Cards or as co-processors to be applied in both server and edge computing solutions to accelerate AI tasks. The general market need is particularly acute for data center and cloud computing industries where major pain points are performance bottlenecks and high costs due to custom chips or reliance on graphic processing units. The core value propositions of the proposed technology are faster compute, programmability at run-time, and easier integration with existing software to enable execution of popular machine learning frameworks.This Small Business Innovation Research Phase (SBIR) Phase I project centers around a novel computing approach where computing and memory elements are parallel and distributed, and interconnection between computing elements is flexible. The project develops an integrated circuit chip that can be reconfigured at run-time to behave as a custom application-specific integrated circuit for each running Artificial Intelligence (AI) application to deliver the optimal performance. It will overcome the memory bottleneck that traditional computing technologies face where data needs to be continuously loaded to and from memory. The proposed technology also addresses the adaptivity challenge for evolving AI models and datasets. The proposed activities include a chip fabrication using a 28nm commercial semiconductor foundry process, extensive benchmarking of the new technology for scalability, adaptability to data size and shape, and research on a software interface to execute codes developed by existing machine learning frameworks in the new chip. The prototype chip is expected to demonstrate distributed and parallel computing capabilities along with dynamic reconfigurability. The benchmarking work is anticipated to reveal at least an order of magnitude improvement over more conventional graphics processing unit based approaches.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.