Collaborative Research: CISE-MSI: DP: SaTC: Ensemble of Countermeasures for Malicious Thermal Sensors Attacks

该奖项的全部或部分资金来自《2021年美国救援计划法案》(公法117-2)。现代集成电路(IC)的设计者利用第三方生产的预先设计的知识产权(IP)元件来降低成本和缩短上市时间。虽然这种方法降低了IC的生产成本，但恶意攻击者可以通过在最终产品中插入硬件特洛伊木马(HT)来篡改制造过程。例如，根据一家匿名美国国防承包商的知名报告，在一些商业处理器中发现了隐藏的杀死开关。这项提议针对的是一种新的安全威胁，该威胁源于硬件感染的热传感器。用于动态功率和热管理的热传感器可能会受到HTS的危害，进而严重影响目标IC的安全性、可靠性和性能。解决这样的安全漏洞对广泛的计算系统具有积极影响。大量潜在的受害者系统，如边缘计算设备、移动智能手机、可穿戴系统、数据中心和超级计算机，表明迫切需要应对这一新威胁。仅在IC开发生命周期的一个阶段(例如，设计、测试或运行时)工作的HT检测方法具有重大限制。由于集成电路中有数十亿个门，因此由于可伸缩性问题，设计时的HT检测方法不实用。测试时间方法在很大程度上依赖于对IC功率和热分布的统计分析。但是，由于占地面积较小，他们无法检测到小尺寸的HTS。运行时方法需要一个始终运行的监视器来区分传感器读数，这可能会有很大的开销。该项目开发了一系列新的对策，在测试时和运行时合作解决该问题，以实现IC所需的安全性和可靠性。如果由于超线程的占用空间可以忽略不计，测试时方法无法检测到受超线程感染的传感器(S)，则运行时方法可以检测并隔离受损的传感器(S)。此外，引入的方法可以准确估计分配给隔离热传感器的现场温度，以便热和电源管理例行扫描继续正常运行。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

This award is funded in whole or in part under the American Rescue Plan Act of 2021 (Public Law 117-2).Designers of modern Integrated Circuit (IC) take advantage of pre-designed Intellectual Property (IP) components produced by third parties to reduce costs and time to market. Although this approach decreases the IC production costs, a malicious adversary could tamper with the manufacturing process by inserting Hardware Trojans (HT) into the final product. For example, according to a well-known report by an anonymous US defense contractor, hidden kill switches were found in some commercial processors. This proposal targets a new security threat originating from hardware-infected thermal sensors. Thermal sensors used for dynamic power and thermal management can be compromised by HTs, which in turn, seriously impacts the target IC's security, reliability, and performance. Addressing such a security vulnerability has positive impacts on a wide range of computing systems. The large spectrum of potential victim systems, e.g., edge computing devices, mobile smartphones, wearable systems, data centers, and supercomputers, indicates the utmost need to address this new threat. HT detection methods working at only one stage of the IC development life-cycle (e.g., design-, test-, or runtime) have major limitations. Having billions of gates in an IC makes design-time HT detection methods impractical due to scalability issues. Test-time methods rely heavily on a statistical analysis of the IC power and thermal profiles. But, they cannot detect small-size HTs due to the small footprints. Run-time methods require an always-running monitor to discriminate sensor readings, which could have large overheads. This project develops an ensemble of novel countermeasures that address the problem cooperatively at test-time and run-time to attain the required security and reliability of ICs. If test-time methods fail in detecting the HT infected sensor(s) due to a negligible footprint of an HT, then run-time methods can detect and isolate the compromised sensor(s). Furthermore, the introduced methods can accurately estimate the temperature of the spot assigned to the isolated thermal sensor so that the thermal and power management routine scan continues to function properly.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.