Collaborative Research: SaTC: CORE: Small: SOCIAL: System-on-Chip Information Flow Validation under Asynchronous Events

协作研究：SaTC：CORE：小型：SOCIAL：异步事件下的片上系统信息流验证

• 批准号: 2223046
• 负责人: Kanad Basu
• 金额: $ 29.04万
• 依托单位: University of Texas at Dallas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-10-01 至 2025-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2223046&HistoricalAwards=false
• 关键词: Collaborative; Research; SaTC; CORE; Small

We live in an era where smart, connected computing devices pervade many critical applications, including transportation systems, industrial automation, health and biomedical systems, etc. Naturally, these devices create, process, and exchange significant sensitive information. Unauthorized or malicious access to these assets can result in disastrous consequences, including loss of human life in the case of health monitoring systems. The goal of this project is to create a comprehensive infrastructure for information flow validation, i.e., ensuring that sensitive assets in modern System-on-Chip designs cannot be accessed or corrupted by an unauthorized or untrusted agent. The ove r-arching goal is to develop a scientific foundation and a comprehensive automated framework of integrated tools for systematically addressing the spectrum of challenges in information flow validation. The research objectives are tightly integrated into teaching and outreach activities, in the form of new curriculum development, organizing security competitions in premier conferences, recruitment of female and underrepresented minority students, and involving high-school graduates in research. The project has three technical objectives. The first objective is to develop a core foundation for information flow analysis that accounts for real-world complexities. In particular, many hard-to-detect real-world information flow violations result from interruptions of functional flow by a variety of asynchronous events, to subvert the integrity of hardware assets. The project addresses this critical issue by incorporating new, innovative approaches to specify, analyze, and integrate the role of asynchronous events and hardware-firmware interaction within the foundation. The second objective is to develop a comprehensive automated framework of integrated tools for systematically addressing the spectrum of challenges in information flow validation. The project addresses this goal through a combination of dynamic and formal analysis techniques that draw inspiration from advances in formal methods, testing, and machine learning. Third, the project targets smooth integration of the analysis infrastructure with industrial validation flows.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

我们生活在一个智能互联计算设备遍布许多关键应用的时代，包括运输系统、工业自动化、健康和生物医学系统等。 未经授权或恶意访问这些资产可能导致灾难性后果，包括健康监测系统的人员生命损失。该项目的目标是为信息流验证创建一个全面的基础设施，即，确保现代片上系统设计中的敏感资产不会被未经授权或不受信任的代理访问或破坏。总体目标是开发一个科学基础和一个综合工具的全面自动化框架，以系统地解决信息流验证中的一系列挑战。研究目标与教学和外联活动紧密结合，其形式包括制定新的课程、在重要会议上组织安保竞赛、招聘女性和代表性不足的少数民族学生以及让高中毕业生参与研究。该项目有三个技术目标。第一个目标是为信息流分析开发一个核心基础，以解释现实世界的复杂性。特别是，许多难以检测的现实世界的信息流违规行为是由于各种异步事件中断功能流而导致的，从而破坏了硬件资产的完整性。该项目通过采用新的创新方法来指定，分析和集成异步事件和基础内硬件-固件交互的作用来解决这个关键问题。 第二个目标是开发一个综合工具的全面自动化框架，以系统地解决信息流验证中的一系列挑战。该项目通过结合动态和形式化分析技术来实现这一目标，这些技术从形式化方法、测试和机器学习的进步中汲取灵感。第三，该项目的目标是分析基础设施与工业验证流程的顺利整合。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

System-On-Chip Information Flow Validation Under Asynchronous Resets

异步复位下的片上系统信息流验证

• DOI: 10.1109/tcad.2024.3376596
• 发表时间: 2024
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Miftah, Samit S.;Raj, Kshitij;Meng, Xingyu;Ray, Sandip;Basu, Kanad
• 通讯作者: Basu, Kanad