NSF Convergence Accelerator Track I: Building a Sustainable, Innovative Ecosystem for Microchip Manufacturing
NSF Convergence Accelerator Track I: Building a Sustainable, Innovative Ecosystem for Microchip Manufacturing
批准号:
2236093
负责人:
Anuradha Agarwal
金额:
$75.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2022
资助国家:
美国
项目状态:
已结题
起止时间:
2022-12-15 至 2023-11-30
中文摘要
微电子技术是从通信和计算到传感和成像等功能的普遍解决方案,适用于从洗衣机到汽车和大型数据中心的产品。晶体管尺寸缩放降低了能耗,同时提高了速度和功能。为了保持性能缩放:i)迭代技术变化是不够的,ii)在劳动力质量、材料关键性和制造废水方面的供应链可持续性没有固有的缩放向量。美国面临的经济风险从未如此之大,也很少如此依赖于一项特定的技术发展。晶体管/芯片缩放的终结需要一种新的芯片/封装缩放模式。该研究计划将为微电子封装供应链创建一个正式的行业/政府/学术基础设施,称为微电子制造可持续发展计划(MMSP),该计划将提供共识政策建议,技术目标和时间表,以及芯片/封装缩放的教育和劳动力发展产品;并将制作一个新的大带宽芯片封装的原型。MMSP将由六个融合团队(技术、劳动力、制造、供应链、材料关键性、路线图)领导,以实现:(a)微电子规模化的创新封装原型;(b)材料、加工、设计和可持续性规模化的行业技术路线图;(c)面向信息和汽车行业的集成电路芯片中材料关键性、工艺废水和从摇篮到摇篮的能源消耗的大挑战可持续性研究。(d)材料特性、工艺工具和劳动力技能数据库,以指导包装创新。MMSP将:(i)向行业研发部门提供创新原型;(ii)采用敏捷的持续教育方法,在美国微电子行业的人力资本教育和培训中拥抱多样性、公平性、包容性和可及性;(iii)建立K-12科学、技术、工程和数学意识,以支持下一代工程师和技术人员的关键渠道;(iv)与传统黑人学院和大学以及西班牙裔服务机构合作;(五)建立不同的工作组,以制定技术和教育路线图。拟议的项目还包括三个主要的技术组成部分。(1)电子-光子封装(EPP)研究:价值4000亿美元的半导体产业供应链将如何从芯片缩放到新的封装缩放平台?从纯电子到光子学应用的专家团队是否可以共同创建通用术语表、设计基础设施和供应链对齐?MMSP是由集成光电子系统国际路线图(IPSR-I)联盟推动的,该联盟是一个构建通用制造平台的论坛,并建立学习曲线,以确定研发的性能/成本效益。全球电子/光子行业已承诺为微电子供应链构建具有可持续性指标的EPP路线图。第一阶段的研究将包括创新EPP设计的可行性演示,以将封装I/O扩展到1 pb /s的数据传输速率。(2)可持续性属性和边界:可持续性是大批量制造的关键“小星球边界”。第一阶段白皮书研究将指导EPP路线图任务,以评估材料、劳动力、生命周期和能源如何成为供应链限制资源;路线图版本将预测中断,并指定工程、经济、社会和政策约束与研究、设计和制造过程为基础的成本模型之间的权衡。(3)劳动力敏捷继续教育:技术转型带来以下风险:(1)企业的业务和可持续性主张;(ii)工人的职业生涯;(三)现有技术的兼容性。将学习科学与制造创新相结合将使研究发现转化为新的包装/测试设计教育计划(第一阶段概述课程)。麻省理工学院的教育和应用原型实验室(LEAP)将通过其现有的混合教学策略培训2年制和4年制的大学生和提高在职工人的技能:(a)大规模开放在线课程(概念学习);(b)虚拟现实模拟(加强概念学习,程序技能的预训练);(c)现场训练营的动手实验(加强程序/概念学习)。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Microelectronics technology is the pervasive solution across functions ranging from communications and computation to sensing and imaging, for products ranging from washing machines to automobiles and mega-data centers. Transistor dimensional scaling has reduced energy consumption and increased speed and functionality, simultaneously. To maintain performance scaling: i) iterative technology change is insufficient, and ii) supply chain sustainability in terms of workforce quality, materials criticality, and manufacturing effluent has no inherent scaling vector. Economic risk for the nation has never been so large, and rarely been so dependent on a particular technology evolution. The end of transistor/chip scaling requires a new chip/package scaling paradigm. This research program will create a formal industry/government/academic infrastructure called the Microelectronics Manufacturing Sustainability Program (MMSP) for the microelectronics packaging supply chain that will deliver consensus policy recommendations, technology goals and timelines, as well as education and workforce development products in chip/package scaling; and will prototype a new massive-bandwidth chip package. MMSP will be led by six Convergence Teams (Technology, Workforce, Manufacturing, Supply Chain, Materials Criticality, Roadmap) to realize:(a) Innovative packaging prototypes for scaling microelectronics (b) an industry Technology Roadmap for materials, processing, design, and sustainability scaling(c) Grand Challenge sustainability studies of materials criticality, process effluent and cradle-to grave energy consumption in IC chips for information and automotive industries, and (d) Databases of materials properties, process tools, and workforce skills to guide packaging innovation. MMSP will: (i) inform industry R&D with innovative prototypes; (ii) embrace Diversity, Equity, Inclusion and Accessibility with education and training for human capital of the US microelectronics industry, using an agile continuous education methodology; (iii) create K-12 Science, Technology, Engineering and Mathematics awareness to support a critical pipeline for the next-generation of engineers and technicians; (iv) engage with Historically Black Colleges and Universities and Hispanic Serving Institutions; and (v) build diverse working groups for the creation of technology and education roadmaps. There will also be three major technical components to the proposed project. (1) Electronic-Photonic Packaging (EPP) Research: How will a $400B semiconductor industry supply chain transition from chip-scaling to a new package-scaling platform? Can teams of experts who bridge applications from pure electronics to photonics jointly create a common glossary, design infrastructure, and supply chain alignment? MMSP is driven by the Integrated Photonics Systems Roadmap-International (IPSR-I) Consortium: a forum to construct a common manufacturing platform and establish a learning curve to identify performance/cost benefits of research and development Grand Challenges. Global electronic/photonic industries have committed to construction of an EPP Roadmap for the microelectronics supply chain with sustainability metrics. Phase 1 research will include feasibility demonstration of innovative EPP designs for scaling package I/O to 1 Petabit/second data transfer rates. (2) Sustainability Attributes & Boundaries: Sustainability is the critical ‘small planet frontier’ for high volume manufacturing. Phase 1 white paper studies will guide EPP Roadmap tasks to assess how materials, workforce, life-cycle, and energy become supply chain limiting resources; the Roadmap releases will anticipate disruptions and specify trade-offs in engineering, economic, social, and policy constraints with research, design, and manufacturing Process-Based Cost Models. (3) Workforce Agile Continuous Education: Technology transitions introduce risks to: (i) firms’ business and sustainability propositions; (ii) worker careers; and (iii) incumbent technology compatibility. Converging Learning Science with Manufacturing Innovation will enable research discovery to translate into a new Design for Packaging/Test education program (Phase 1 outlines curriculum). MIT’s Lab for Education and Application Prototypes (LEAP) will train 2-year and 4-year college students and upskill incumbent workers by its extant blended instruction strategy: (a) Massive Open Online Courses (conceptual learning); (b) Virtual Reality sims (fortify conceptual learning, pre-train in procedural skills); (c) hands-on labs (fortify procedural/conceptual learning) in on-site bootcamps.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(1)
专著(0)
科研奖励(0)
会议论文
High density vertical optical interconnects for passive assembly
用于无源组装的高密度垂直光学互连
DOI:
10.1364/oe.475726
发表时间:
2023
期刊:
Optics Express
影响因子:
3.8
作者:
[Weninger, Drew, Serna, Samuel, Jain, Achint, Kimerling, Lionel, Agarwal, Anuradha]
通讯作者:
Agarwal, Anuradha
NSF Convergence Accelerator Track I: FUTUR-IC: A Sustainable Microchip Manufacturing Alliance
-
批准号:2345076
-
项目类别:Cooperative Agreement
-
资助金额:$500.0万
-
财政年份:2023
-
负责人:Anuradha Agarwal
-
依托单位:
海外基金