CAREER: A Framework for Co-design and Optimization of Programmable Hardware Accelerators and Compilers

职业：可编程硬件加速器和编译器协同设计和优化的框架

• 批准号: 2238006
• 负责人: Priyanka Raina
• 金额: $ 50万
• 依托单位: Stanford University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-03-15 至 2028-02-29
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2238006&HistoricalAwards=false
• 关键词: CAREER; Framework; Co; design; Optimization

Creating energy-efficient computing systems is essential for achieving the societal goal of sustainability. As the semiconductor technology scaling predicted by Moore’s law slows down, domain-specific hardware accelerators, i.e., hardware blocks specialized to do certain tasks very well, will play an increasingly important role in improving the performance and energy-efficiency of computing systems. Modern mobile chips have dozens of accelerators for applications such as image processing, video coding, graphics, neural networks etc. to achieve low power consumption and fast processing speeds. However, with advances in machine learning, these applications are changing at a rapid pace. Maintaining high performance and energy-efficiency requires that hardware accelerators, compilers, and applications evolve together in lockstep. Unfortunately, existing methodologies to achieve this involve significant manual effort. Large engineering teams study the accelerator architecture in detail and modify the compiler in an ad hoc manner, leveraging low-level libraries to target specific hardware features. Because of the large overhead in maintaining the software stack, it remains challenging to accelerate new domains or existing domains as they evolve. What is needed is a structured approach for generating programmable accelerators and for updating the software compiler as the accelerator architecture evolves with the applications. This project proposes a design-space exploration and optimization framework that automatically generates accelerator architectures that approach the efficiencies of hand-designed ones, with a significantly lower design effort for both hardware and compiler generation. This work can impact how hardware-software system design is done today in the industry, by reducing the time to market for products and creating more productive design teams. Moreover, the openly shared curriculum developed as a part of this work will ensure equitable access to educational opportunities and help create a diverse, globally competitive semiconductor workforce. The research goal of this project is to create a framework for automated co-design and optimization of domain-specific hardware accelerators and compilers. The framework will have three components: (1) an automated accelerator processing element (PE) design space optimization tool based on frequent subgraph mining and merging, (2) an accelerator memory element optimization tool for both dense and sparse applications, and (3) an auto-scheduler for automatically determining the best mapping of an application to the accelerator. These tools will be used to design, optimize and prototype in silicon a unified programmable accelerator for both dense application domains such as image processing and machine learning and sparse application domains such as graph analytics, and demonstrate energy-efficiency and performance metrics that significantly beat general purpose architectures and approach application-specific integrated circuits. The proposed approach uses several techniques, distinct from prior work, to achieve automatic accelerator-compiler co-design and optimization. First, it allows any change in the hardware specification to automatically propagate into the compiler with no manual effort. This unique property is the key to enabling large-scale design space exploration of accelerators. Without it, one would have to manually update the application compiler with every hardware change, greatly limiting the number of design points one can explore. Second, the proposed framework for automated PE optimization for accelerators generates efficient PE architectures from the application graphs themselves, using frequent subgraph mining and merging. This approach is quite different from prior work, which does not perform application-driven optimization but rather searches over many possible PE parameter values. As a result, this approach promises to be much more sample-efficient and faster versus prior work. Finally, as opposed to existing commercial high level synthesis tools and compilers for programmable accelerators which require the user to provide low-level scheduling directives in the application code, the auto-scheduler proposed will automatically search for the best mapping of an application to the programmable accelerator, greatly improving user productivity.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

创建节能计算系统对于实现可持续发展的社会目标至关重要。随着摩尔定律预测的半导体技术规模放缓，特定于领域的硬件加速器，即专门用于非常好地完成某些任务的硬件块，将在提高计算系统的性能和能效方面发挥越来越重要的作用。现代移动芯片有几十个加速器，用于图像处理、视频编码、图形、神经网络等应用，以实现低功耗和快速处理速度。然而，随着机器学习的进步，这些应用正在以快速的速度发生变化。要保持高性能和高能效，需要硬件加速器、编译器和应用程序同步发展。不幸的是，实现这一点的现有方法需要大量的手动工作。大型工程团队详细研究加速器体系结构，并以特别的方式修改编译器，利用低级库来瞄准特定的硬件功能。由于维护软件堆栈的开销很大，因此随着新域或现有域的发展，加速它们的速度仍然具有挑战性。所需要的是一种用于生成可编程加速器并且用于随着加速器体系结构随着应用的发展而更新软件编译器的结构化方法。这个项目提出了一个设计空间探索和优化框架，它自动生成接近手工设计的加速器体系结构的效率，硬件和编译器生成的设计工作量都大大降低。这项工作可以通过缩短产品上市时间和创建更高效的设计团队来影响当今行业中硬件-软件系统设计的方式。此外，作为这项工作的一部分而开发的公开共享课程将确保公平地获得教育机会，并有助于培养一支多元化的、具有全球竞争力的半导体劳动力队伍。该项目的研究目标是为特定领域的硬件加速器和编译器创建一个自动化协同设计和优化的框架。该框架将包括三个组件：(1)基于频繁子图挖掘和合并的自动加速器处理元件(PE)设计空间优化工具；(2)用于密集和稀疏应用的加速器存储元件优化工具；以及(3)用于自动确定应用到加速器的最佳映射的自动调度器。这些工具将用于在硅中设计、优化和制作适用于图像处理和机器学习等密集应用领域和图形分析等稀疏应用领域的统一可编程加速器，并展示显著优于通用架构和接近专用集成电路的能效和性能指标。与以往的工作不同，该方法使用多种技术来实现加速器-编译器的自动协同设计和优化。首先，它允许硬件规范中的任何更改自动传播到编译器中，而不需要手动操作。这一独特的特性是实现加速器大规模设计空间探索的关键。如果没有它，人们将不得不在每次硬件更改时手动更新应用程序编译器，这极大地限制了人们可以探索的设计点的数量。其次，提出的加速器PE自动优化框架通过频繁子图挖掘和合并，从应用图本身生成高效的PE体系结构。这种方法与以前的工作有很大不同，以前的工作不执行应用程序驱动的优化，而是搜索许多可能的PE参数值。因此，这种方法有望比以前的工作更具样本效率和速度。最后，与现有商业可编程加速器高级综合工具和编译器需要用户在应用程序代码中提供低级调度指令不同，所提出的自动调度器将自动搜索应用程序到可编程加速器的最佳映射，极大地提高用户生产力。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays

Canal：用于粗粒度可重构阵列的灵活互连生成器

• DOI: 10.1109/lca.2023.3268126
• 发表时间: 2023
• 期刊: IEEE Computer Architecture Letters
• 影响因子: 2.3
• 作者: Melchert, Jackson;Zhang, Keyi;Mei, Yuchen;Horowitz, Mark;Torng, Christopher;Raina, Priyanka
• 通讯作者: Raina, Priyanka

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra

• DOI: 10.1109/jssc.2023.3313116
• 发表时间: 2024-03
• 期刊: IEEE Journal of Solid-State Circuits
• 影响因子: 5.4
• 作者: Kathleen Feng;Taeyoung Kong;Kalhan Koul;J. Melchert;Alex Carsello;Qiaoyi Liu;Gedeon Nyengele;Maxwell Strange;Kecheng Zhang;Ankita Nayak;Jeff Setter;James J. Thomas;Kavya Sreedhar;Po-Han Chen;Nikhil Bhagdikar;Zachary Myers;Brandon D'Agostino;Pranil Joshi;Stephen Richardson;Christopher Torng;Mark Horowitz;Priyanka Raina

APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis

• DOI: 10.1145/3582016.3582070
• 发表时间: 2023-03
• 期刊: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3
• 作者: J. Melchert;Kathleen Feng;Caleb Donovick;Ross G. Daly;Ritvik Sharma;Clark W. Barrett;M. Horowitz;P. Hanrahan;Priyanka Raina