CAREER: Universal Design Automation Framework for Analog Integrated Systems

职业:模拟集成系统的通用设计自动化框架

基本信息

  • 批准号:
    2239033
  • 负责人:
  • 金额:
    $ 52.76万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Continuing Grant
  • 财政年份:
    2023
  • 资助国家:
    美国
  • 起止时间:
    2023-01-01 至 2027-12-31
  • 项目状态:
    未结题

项目摘要

Analog integrated circuits (ICs) are indispensable components in modern electronics. They allow computers to interact with the real world by performing key functions such as sensor interfacing, signal conditioning, power delivery, and energy harvesting. Their importance keeps growing as these functions are increasingly essential in the next-generation artificial intelligence, automotive, and medical applications that seek to sense, learn, and act anytime, anywhere. To meet the surging market demand, it is critical to ensure the development and production of analog ICs are agile, low-cost, and high-quality. However, this goal is currently being hindered by two grand challenges. On the technical level, the analog IC design practice in the industry to date remains a slow, experience-demanding manual process due to the lack of a general-purpose, reliable, and scalable analog design automation tool. This deficiency imposes a severe bottleneck for cost and design time reduction. Additionally, societal factors include experienced designers retiring fast while younger generations may shy away from pursuing an IC designer career. A paradigm shift in analog IC design practices is needed to prevent this analog IC productivity crisis from turning into a pressing roadblock for technology development and industry growth. To that end, this CAREER research aims to establish and validate a novel general-purpose analog IC design automation flow that overcomes the existing productivity barrier. The research will lead to a game-changing tool that allows designers to turn their ideas into circuit structures for a wide range of analog systems in a LEGO-like plug-and-play manner, improves their design reliably with machine learning, and generates fabrication-ready mask layouts swiftly. It will not only bring radical improvement to analog IC productivity and accelerate new technology development but also create a far-reaching impact on the competitiveness of the US semiconductor industry. The integrated education activities will also revolutionize IC technology education at both undergraduate and graduate levels, facilitating workforce revitalization.Analog IC design is conventionally deemed a highly ad-hoc practice, where high-level abstraction is hardly feasible. Although analog design automation (ADA) has received growing attention in the past decade, there is a lack of an ADA solution that combines versatile system-scale handling capabilities, reliability, and sufficient human interactions. In this research, the investigator identifies a path of breakthrough. This framework is established through endeavors in three research thrusts. (1) Development of an innovative unified analog system modeling method, which can describe a wide range of analog systems in the form of linear filter models built from a common set of basic operation cells. This method includes an intelligent synthesis algorithm and a user interface to aid designers in turning their thoughts into models. (2) Development of a soft cell concept, which performs on-the-fly circuit creation for the operation cell. This idea will address the reliability issue through a software-hardware co-design methodology. (3) Development of an early performance prediction mechanism that guides designers to achieve better results. The framework will be thoroughly validated by applying it to a practical biomedical system-on-chip design and demonstrating competitive circuit performances via real silicon measurements. In essence, the project closely incorporates the interdisciplinary efforts of modeling, circuit design, and algorithm, a unique path in ADA research. The generated knowledge bridges the circuit design community and the electronic design automation (EDA) community to catalyze closer collaboration and co-development.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
模拟集成电路(IC)是现代电子产品中不可缺少的部件。它们允许计算机通过执行诸如传感器接口、信号调节、功率输送和能量收集等关键功能与真实的世界进行交互。它们的重要性不断增长,因为这些功能在下一代人工智能、汽车和医疗应用中越来越重要,这些应用寻求随时随地感知、学习和行动。为了满足不断增长的市场需求,确保模拟IC的开发和生产敏捷、低成本和高质量至关重要。然而,这一目标目前正受到两大挑战的阻碍。在技术层面上,由于缺乏通用、可靠、可扩展的模拟设计自动化工具,迄今为止业界的模拟IC设计实践仍然是一个缓慢、需要经验的手工过程。这一缺陷对降低成本和缩短设计时间造成了严重的瓶颈。此外,社会因素包括经验丰富的设计师快速退休,而年轻一代可能会回避追求IC设计师职业。模拟IC设计实践的范式转变是必要的,以防止这种模拟IC生产力危机变成技术发展和行业增长的紧迫障碍。为此,这项CAREER研究旨在建立和验证一种新的通用模拟IC设计自动化流程,以克服现有的生产力障碍。这项研究将带来一种改变游戏规则的工具,使设计人员能够以类似乐高的即插即用方式将他们的想法转化为各种模拟系统的电路结构,通过机器学习可靠地改进他们的设计,并迅速生成可制造的掩模布局。它不仅将带来模拟集成电路生产力的根本性提高和加速新技术的发展,而且将对美国半导体产业的竞争力产生深远的影响。集成教育活动还将彻底改变本科和研究生阶段的IC技术教育,促进劳动力的振兴。模拟IC设计通常被认为是一种高度特设的实践,高级抽象几乎不可行。尽管模拟设计自动化(ADA)在过去十年中受到越来越多的关注,但缺乏一种结合了通用系统规模处理能力、可靠性和足够的人机交互的ADA解决方案。在这项研究中,研究人员确定了一条突破之路。这个框架是通过三个研究重点的努力建立的。(1)开发了一种创新的统一模拟系统建模方法,该方法可以以线性滤波器模型的形式描述各种模拟系统,该模型是从一组通用的基本操作单元构建的。该方法包括一个智能合成算法和一个用户界面,以帮助设计师将他们的想法转化为模型。(2)开发软单元概念,为操作单元执行动态电路创建。这一想法将通过软硬件协同设计方法来解决可靠性问题。(3)开发早期性能预测机制,指导设计人员实现更好的结果。该框架将被彻底验证,将其应用到一个实际的生物医学片上系统的设计,并通过真实的硅测量展示竞争力的电路性能。从本质上讲,该项目紧密结合了建模,电路设计和算法的跨学科努力,这是ADA研究的独特途径。该奖项反映了NSF的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。

项目成果

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Shaolan Li其他文献

A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library
从数字标准单元库合成的 60-fJ/步、基于 11-ENOB VCO 的 CTDSM
A 0.029MM2 17-FJ/Conv.-Step CT $DeltaSigma$ ADC with 2nd-Order Noise-Shaping SAR Quantizer
具有二阶噪声整形 SAR 量化器的 0.029MM2 17-FJ/Conv.-Step CT $DeltaSigma$ ADC
Screening Therapeutic Core Genes in Sepsis Using Network Pharmacology and Single-Cell RNA Sequencing
  • DOI:
    10.1007/s10528-025-11075-6
  • 发表时间:
    2025-03-20
  • 期刊:
  • 影响因子:
    1.600
  • 作者:
    Guihong Chen;Wen Zhang;Chenglin Wang;Yingchun Hu;Shaolan Li
  • 通讯作者:
    Shaolan Li
A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation
采用单放大器 EF-CIFF 结构的 13.8ENOB 全动态三阶噪声整形 SAR ADC,具有硬件复用 kT/C 噪声消除功能

Shaolan Li的其他文献

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