SBIR Phase I: Liquid-Enabled Advanced Pitch (LEAP) Semiconductor Manufacturing
SBIR Phase I: Liquid-Enabled Advanced Pitch (LEAP) Semiconductor Manufacturing
批准号:
2304119
负责人:
Phil Hustad
金额:
$27.5万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2023
资助国家:
美国
项目状态:
已结题
起止时间:
2023-07-15 至 2024-06-30
中文摘要
这个小型企业创新研究(SBIR)第一阶段项目的更广泛的商业影响是半导体制造材料和工艺的开发,这将促进摩尔定律的发展,并有助于加强国内半导体制造能力和能力。最近的供应链问题困扰着半导体行业,并对整个美国经济产生了连锁反应。大多数先进的半导体制造能力都在美国以外,最近的短缺突显出,为了美国的经济活力以及国家安全和供应链弹性,需要国内代工厂。2019年,美国半导体代工厂直接雇佣了184,600名工人,低于2001年的292,100人(-37%)。制造业工作岗位的主要流失归因于离岸铸造厂的使用。目前,美国半导体制造仅占全球产能的1%,80%的美国半导体制造产能是200毫米(8英寸)格式,这与最先进的高性能工艺不兼容,将产量限制在65纳米节点。该项目将提高目前在美国建立的铸造厂的竞争力,并提高在建铸造厂的绩效。该项目旨在开发和验证几种所需材料的性能,以实现一种新的半导体制造工艺的集成,该工艺能够将当前尖端半导体芯片制造工艺的特征密度提高一倍。该解决方案还可以简化整个制造流程,而不需要密集的资本支出。在该项目结束时,开发的材料的性能和由此产生的制造改进将在8英寸和12英寸格式上展示。该工艺开始于在化学放大的抗蚀剂上进行常规光刻以限定浮雕图案。然后,沟槽材料被涂覆在图案的顶部并扩散到图案中,在抗蚀剂的侧壁处创建了一层自对准的极性切换材料。然后应用掩膜来填充图案中的开口,并显示最终的节距加倍图案。扩散控制工艺实现了与替代工艺类似的结果,而不需要昂贵的工具升级。该技术可以将规范光刻方法扩展多达2个节点,降低80%以上的生产成本,并减少图形误差以提高成品率。重要的是,该过程适用于8英寸晶圆,为较老的晶圆带来了先进的节点维度。该奖项反映了NSF的法定使命,并通过使用基金会的智力优势和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase I project is the development of materials and processes for semiconductor manufacturing that will enable the progression of Moore’s Law and help to strengthen domestic semiconductor manufacturing capacity and capability. Recent supply chain issues have plagued the semiconductor industry, and this has had ripple effects throughout the American economy. The majority of advanced semiconductor manufacturing capacity is outside of the U.S. and this recent shortage has highlighted the need for domestic foundries both for economic vitality in the U.S. as well as national security and supply chain resiliency. In 2019, American semiconductor foundries directly employed 184,600 workers, down from 292,100 (-37%) in 2001. The main loss of manufacturing jobs was attributed to the utilization of offshore foundries. Currently, U.S. semiconductor manufacturing represents just 1% of global capacity and 80% of U.S. semiconductor manufacturing capacity is in the 200 mm (8-inch) format, which is not compatible with the most advanced, high-performance processes, limiting production to 65 nm nodes. This project will increase the competitiveness of currently established U.S.-based foundries as well as increase the performance of foundries that are under construction. This project seeks to develop and validate the performance of several required materials to enable the integration of a novel semiconductor manufacturing process that has the capability to double the density of features in current cutting-edge semiconductor chip manufacturing processes. This solution may also simplify the overall manufacturing process, without the need for intensive capital expenditures. At the conclusion of this project, the performance of the developed materials and the resulting manufacturing improvement will be demonstrated on both 8-inch and 12-inch formats. The process begins with conventional photolithography on a chemically amplified resist to define a relief pattern. A Trencher material is then coated on top of and diffused into the pattern, creating a self-aligned layer of polarity-switched material at the sidewalls of the resist. A Masker is then applied to fill the openings in the pattern, and the final pitch-doubled pattern is revealed. The diffusion-controlled process achieves a similar result to alternative processes without the need for expensive tool upgrades. The technology can extend canonical lithography methods by up to 2 nodes, reduce production costs by more than 80%, and reduce patterning errors to improve yield. Importantly, the process is applicable to 8-inch wafers, bringing advanced node dimensionality to older fabs.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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