SBIR Phase I: A Mixed-Computation Neural Network Acceleration Stack for Edge Inference

这个小企业创新研究（SBIR）第一阶段项目的更广泛/商业影响是通过减少训练神经网络和在边缘执行推理的碳排放来提高人工智能的可持续性。此外，该技术将为边缘推理（包括个人健康、高级数据分析和知情决策）产生新的应用和用例，从而显著改善人们的生活和福祉。商业潜力巨大（即每年数百亿美元），对美国高科技产业的潜在经济效益也是如此。这个小企业创新研究（SBIR）第一阶段项目旨在利用优化设计和配置的硬件资源开发混合计算神经网络加速堆栈。这种加速堆栈支持神经网络推理引擎的异构硬件实现，从而可以通过使用不同的数字系统和不同的精度级别来完成各种网络层所需的计算。因此，与使用16位浮点计算的同构网络硬件实现相比，加速堆栈可以实现非常高的推理速度和能源效率，同时保持推理精度。为了支持该边缘推理加速器的设计、优化和运行时效率，需要一套完整的软件和设计自动化工具，包括用于神经网络架构优化和训练的蒸馏器，用于生成非常大且复杂的布尔和多值逻辑函数的优化门级实现的逻辑合成器，用于生成和调度在目标结构上执行的控制流和数据路径指令的编译器。并且还将提供一个用于编排数据移动的运行时系统。由此产生的边缘推理加速器将部署在资源受限、能源有限和成本敏感的边缘设备上。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase I project is to improve the sustainability of artificial intelligence by reducing carbon emissions for training neural networks and performing inference at the edge. Additionally, the technology will spawn new applications and use cases for edge inference (including personal health, advanced data analytics, and informed decision-making), resulting in significant improvements in people's lives and well-being. The commercial potential is substantial (i.e., tens of billions of dollars annually), as are the potential economic benefits to US high-technology industries.This Small Business Innovation Research (SBIR) Phase I project sets out to develop a mixed-computation neural network acceleration stack utilizing optimally designed and provisioned hardware resources. This acceleration stack empowers a heterogeneous hardware realization of a neural network inference engine whereby computations required in various network layers may be done by using different number systems and different precision levels. The acceleration stack can thus achieve very high inference speed and energy efficiency while maintaining the inference accuracy compared to a homogeneous hardware realization of the network using 16-bit floating point computations. To support the design, optimization, and runtime efficiency of this edge inference accelerator, a full suite of software and design automation tools comprising a distiller for neural network architecture optimization and training, a logic synthesizer for generating optimized gate-level realization of very large and complex Boolean and multi-valued logic functions, a compiler for generating and scheduling control-flow and data path instructions that are executed on the target fabric, and a runtime system for orchestrating data movement will also be provided. The resulting edge inference accelerator will be deployable on resource-constrained, energy-limited, and cost-sensitive edge devices.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.