SBIR Phase I: Analog/Mixed-Signal Integrated Circuit Verification Coverage

这个小企业创新研究（SBIR）第一阶段项目提出了一个模拟验证覆盖系统。今天，广泛接受的正式和基于模拟的技术存在于捕获和测量数字集成电路的测试覆盖率，但是没有相应的模拟集成电路的商业能力。模拟设计人员经常花费大量时间分析和过度测试系统行为，只针对一小部分很容易理解的使用场景，而对状态空间的重要部分则完全没有进行测试。由于模拟电路固有的大设计空间，模拟电路的设计探索问题对实现这样一个系统提出了严峻的挑战。提出的创新解决方案通过确定与特定电路相关的设计空间，然后评估该确定区域的探索完整性来解决此问题。将交付一套原型仪器，用于在模拟/混合信号模拟期间测量覆盖范围。建议的产品将自动解析设计网表，添加仪器，运行用户现有的模拟器，分析仪器的输出，将数据保存到数据库中，并构建覆盖配置文件。通过消除冗余模拟和识别设计空间中没有经过充分测试的区域，该功能提供了改进的生产力和结果质量。该项目的更广泛的影响/商业潜力是通过提高A/MS设计验证的质量，提高首次通过设计的成功率和缩短上市时间来提高美国半导体行业的竞争力。A/MS ASIC设计的复杂性积极遵循摩尔定律，但设计验证方面的创新却没有。更重要的是，通过该项目开发的想法对跨越多个领域之间边界的复杂系统具有更广泛的影响，并且不符合用于数字电路的高度约束验证方法。多领域验证问题包括集成电路与微机电或光电器件结合使用，集成电路在生物医学应用等复杂环境中使用，以及集成电路以创新形式而不是传统包装交付，其中整个交付系统的验证是至关重要的。例如，直接安装在柔性基板上的芯片或包含在可能包括堆叠芯片的多芯片模块中。为了能够广泛地访问小型企业以及分散的工作，例如地理上分布的设计团队或研究工作，可以通过作为早期项目的一部分开发的按需验证基础设施来交付此功能。

This Small Business Innovation Research (SBIR) Phase I project proposes an analog verification coverage system. Today well-accepted formal and simulation-based techniques exist to capture and measure test coverage for digital integrated circuits, but there is no corresponding commercial capability for analog integrated circuits. Analog designers frequently spend much time analyzing and over-testing system behavior for a small set of well understood usage scenarios while leaving significant portions of the state-space completely untested. The design exploration problem for analog circuits presents critical challenges for implementing such a system due to the inherently large design space typical of analog circuits. The proposed innovative solution addresses this issue by determining the design space of relevance for a specific circuit and then assessing the completeness of exploration for that identified area. A prototype set of instruments will be delivered that measure coverage during analog/mixed-signal simulations. The proposed product will automatically parse the design netlist, add the instrumentation, run the user's existing simulator, analyze the output from the instrumentation, save data to a database, and build a coverage profile. This capability provides improved productivity and quality of results by eliminating redundant simulations and identifying areas of the design space that have not been sufficiently tested.The broader impact/commercial potential of this project is to improve the competitiveness of U.S. semiconductor industry by improving the quality of A/MS design verification, improving first pass design success and reducing time-to-market. The complexity of A/MS ASIC design has aggressively followed Moore's law, but innovations in design verification have not. More importantly the ideas being developed through this project have broader implications for complex systems that cross the boundaries between multiple domains and do not conform well to the highly constrained verification methods used for digital circuits. Multiple domain verification problems include integrated circuits used in combination with micro-electromechanical or opto-electronic devices, integrated circuits that are utilized in complex environments such as biomedical applications, as well as integrated circuits that are delivered in innovative forms rather than traditional packages where the verification of the entire delivery system is critical. Examples would include chips mounted directly on flexible substrates or contained within multi-chip modules that may include stacked die. To enable broad accessibility to small businesses as well as dispersed efforts such as geographically distributed design teams or research efforts, this capability can be delivered through an on-demand verification infrastructure being developed as part of an earlier project.