Collaborative Research: DESC: Type I: Towards Reduce- and Reuse-based Design of VLSI Systems with Heterogeneous Integration

合作研究：DESC：类型 I：采用异构集成实现基于缩减和重用的 VLSI 系统设计

• 批准号: 2324945
• 负责人: Vidya Chhabria
• 金额: $ 40万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2324945&HistoricalAwards=false
• 关键词: Collaborative; Research; DESC; Type; Towards

All aspects of computing, spanning from small chips to large datacenters, bear a carbon footprint (CFP) price tag. Although the semiconductor industry has dedicated several decades to making chips smaller, faster, and more energy-efficient, the environmental impact has often been neglected. While technology scaling and electronic design automation (EDA) have facilitated designing energy-efficient very large-scale integrated (VLSI) systems that lower operational CFP, the overall environmental footprint has continued to grow, primarily due to carbon emissions from chip design and manufacturing processes. To ensure the sustainable use of modern computing, it is crucial to develop design techniques that not only meet power, performance, and area (PPA) targets but also consider the CFP. With today's trillion-transistor VLSI systems being designed by heterogeneously integrating a set of chiplets, each corresponding to a single die, onto a substrate to reduce costs, and new design methodologies to support these technologies being rolled out, now is an ideal time to help shape these methodologies to be more sustainable. The novelty of this project lies in paving a path toward sustainable design and manufacturing of VLSI systems through heterogeneous integration (HI). It defines metrics related to CFP and develops simulators and optimizers that integrate with design methodologies to measure and reduce the overall CFP. Inspired by the principles of environmental sustainability—reduce, reuse, and recycle—this project aims to decrease the CFP associated with modern heterogeneous VLSI systems. HI systems offer great potential for sustainable computing by "reducing" carbon emissions through minimized computation required for designing each component from scratch and by "reusing" pre-designed chiplet intellectual property (IP) blocks through hierarchical approaches. Reusing chiplets across multiple designs, implemented in different technology nodes, within the current generation of integrated circuits (ICs) and even in future generations can significantly alleviate the manufacturing CFP. This project develops EDA approaches that (a) measure the carbon impact of heterogeneous VLSI system by building simulators that analyze its CFP across the design, manufacturing, and operational levels of a supply chain; (b) design methods for building high-performance HI systems, a new capability to be developed (since viable HI design flows do not exist today), tuned for efficient computation to reduce design-time carbon; (c) extend methodologies in the design task to incorporate the simulators from the measure task, to optimize the carbon footprint of a design, subject to PPA specifications on the HI design. This project outlines environmentally conscious computing practices by emphasizing the integration of CFP-related metrics into HI design methodologies and brings the community's attention to this critical issue in the semiconductor industry.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

从小芯片到大数据中心的计算的所有方面都带有碳足迹（CFP）的价格标签。尽管半导体行业已专门数十年，以使芯片更小，更快，更节能，但环境影响通常被忽略了。虽然技术缩放和电子设计自动化（EDA）已经准备好设计能节能的非常大规模集成（VLSI）系统，以降低运行CFP，但总体环境足迹持续增长，主要是由于芯片设计和制造过程中的碳排放。为了确保现代计算的可持续使用，开发不仅满足功率，性能和区域（PPA）目标的设计技术至关重要，而且考虑CFP。随着当今的数万亿台式VLSI系统的设计是通过异质化将一组与单个模具相对应的芯片集成到一个基板上以降低成本的基板以及支持这些技术被推出的新设计方法的设计，现在是帮助塑造这些方法更可持续的时机。该项目的新颖性在于通过异质整合（HI）铺平了通往可持续设计和制造VLSI系统的道路。它定义了与CFP相关的指标，并开发了与设计方法集成以测量和减少总体CFP的模拟器和优化器。受环境可持续性原则的启发（还原，再利用和回收利用），该项目旨在减少与现代异构VLSI系统相关的CFP。 HI系统通过最小化从头开始设计每个组件并通过层次结构方法“重新设计”预设的chiplet知识属性（IP）块来“减少”碳排放，从而为可持续计算提供了巨大的潜力。在当前一代的集成电路（IC）甚至在后代中，在多种设计中重复使用多种设计的chiplets，可以大大减轻制造CFP。该项目开发了EDA方法，即（a）通过构建模拟器来衡量异质VLSI系统的碳影响，从而在供应链的设计，制造和运营水平上分析其CFP； （b）用于构建高性能HI系统的设计方法，这是一种新的功能（由于今天不存在可行的HI设计流），并调整了有效的计算以减少设计时间碳； （c）扩展了设计任务中的方法，以将模拟器从测量任务中合并，以优化设计的碳足迹，但根据HI设计的PPA规格。该项目通过强调将与CFP相关的指标集成到HI设计方法中，并在半导体行业中引起社区对这个关键问题的关注来概述了具有环境意识的计算实践。该奖项反映了NSF的法定任务，并通过使用该基金会的智力功能和广泛影响来评估CRITERIA CRITERIA，以评估来表现出珍贵的支持。