Collaborative Research: DESC: Type I: Towards Reduce- and Reuse-based Design of VLSI Systems with Heterogeneous Integration

合作研究：DESC：类型 I：采用异构集成实现基于缩减和重用的 VLSI 系统设计

• 批准号: 2324945
• 负责人: Vidya Chhabria
• 金额: $ 40万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2324945&HistoricalAwards=false
• 关键词: Collaborative; Research; DESC; Type; Towards

All aspects of computing, spanning from small chips to large datacenters, bear a carbon footprint (CFP) price tag. Although the semiconductor industry has dedicated several decades to making chips smaller, faster, and more energy-efficient, the environmental impact has often been neglected. While technology scaling and electronic design automation (EDA) have facilitated designing energy-efficient very large-scale integrated (VLSI) systems that lower operational CFP, the overall environmental footprint has continued to grow, primarily due to carbon emissions from chip design and manufacturing processes. To ensure the sustainable use of modern computing, it is crucial to develop design techniques that not only meet power, performance, and area (PPA) targets but also consider the CFP. With today's trillion-transistor VLSI systems being designed by heterogeneously integrating a set of chiplets, each corresponding to a single die, onto a substrate to reduce costs, and new design methodologies to support these technologies being rolled out, now is an ideal time to help shape these methodologies to be more sustainable. The novelty of this project lies in paving a path toward sustainable design and manufacturing of VLSI systems through heterogeneous integration (HI). It defines metrics related to CFP and develops simulators and optimizers that integrate with design methodologies to measure and reduce the overall CFP. Inspired by the principles of environmental sustainability—reduce, reuse, and recycle—this project aims to decrease the CFP associated with modern heterogeneous VLSI systems. HI systems offer great potential for sustainable computing by "reducing" carbon emissions through minimized computation required for designing each component from scratch and by "reusing" pre-designed chiplet intellectual property (IP) blocks through hierarchical approaches. Reusing chiplets across multiple designs, implemented in different technology nodes, within the current generation of integrated circuits (ICs) and even in future generations can significantly alleviate the manufacturing CFP. This project develops EDA approaches that (a) measure the carbon impact of heterogeneous VLSI system by building simulators that analyze its CFP across the design, manufacturing, and operational levels of a supply chain; (b) design methods for building high-performance HI systems, a new capability to be developed (since viable HI design flows do not exist today), tuned for efficient computation to reduce design-time carbon; (c) extend methodologies in the design task to incorporate the simulators from the measure task, to optimize the carbon footprint of a design, subject to PPA specifications on the HI design. This project outlines environmentally conscious computing practices by emphasizing the integration of CFP-related metrics into HI design methodologies and brings the community's attention to this critical issue in the semiconductor industry.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

计算的各个方面，从小芯片到大型数据中心，都带有碳足迹 (CFP) 价格标签。尽管半导体行业几十年来一直致力于使芯片变得更小、更快、更节能，但对环境的影响却常常被忽视。虽然技术扩展和电子设计自动化 (EDA) 促进了节能型超大规模集成 (VLSI) 系统的设计，从而降低了运行 CFP，但总体环境足迹仍在持续增长，这主要是由于芯片设计和制造过程中的碳排放。为了确保现代计算的可持续利用，开发不仅满足功耗、性能和面积 (PPA) 目标而且还要考虑 CFP 的设计技术至关重要。当今的万亿晶体管 VLSI 系统是通过将一组小芯片（每个小芯片对应一个芯片）异构集成到基板上来设计的，以降低成本，并且支持这些技术的新设计方法正在推出，现在是帮助这些方法变得更加可持续的理想时机。该项目的新颖之处在于通过异构集成（HI）为超大规模集成电路系统的可持续设计和制造铺平了道路。它定义了与 CFP 相关的指标，并开发了与设计方法集成的模拟器和优化器，以测量和降低总体 CFP。受环境可持续性原则（减少、再利用和回收）的启发，该项目旨在减少与现代异构 VLSI 系统相关的 CFP。 HI 系统通过最大限度地减少从头开始设计每个组件所需的计算来“减少”碳排放，并通过分层方法“重用”预先设计的小芯片知识产权 (IP) 块，从而为可持续计算提供了巨大的潜力。在当代集成电路 (IC) 甚至未来几代中，在不同技术节点中实现的多种设计中重复使用小芯片可以显着减轻制造 CFP。该项目开发了 EDA 方法，该方法 (a) 通过构建模拟器来测量异构 VLSI 系统的碳影响，该模拟器在供应链的设计、制造和运营层面分析其 CFP； (b) 构建高性能 HI 系统的设计方法，这是一种有待开发的新功能（因为目前尚不存在可行的 HI 设计流程），并针对高效计算进行调整，以减少设计时的碳排放； (c) 扩展设计任务中的方法，将测量任务中的模拟器纳入其中，以优化设计的碳足迹，并遵守 HI 设计的 PPA 规范。该项目通过强调将 CFP 相关指标集成到 HI 设计方法中，概述了环保计算实践，并引起了社区对半导体行业这一关键问题的关注。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。