Collaborative Research: SHF: Medium: Tiny Chiplets for Big AI: A Reconfigurable-On-Package System

合作研究：SHF：中：用于大人工智能的微型芯片：可重新配置的封装系统

• 批准号: 2403409
• 负责人: Jun Zhang
• 金额: $ 40万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2024
• 资助国家: 美国
• 起止时间: 2024-07-01 至 2028-06-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2403409&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Tiny

As monolithic chips reach their technological and practical limits, the integration of chiplets is emerging as the primary mechanism to continuously scale up processor performance, improve power efficiency, enhance IP reuse at low cost, and expedite time-to-market. This new concept of composable chiplets is particularly appealing to the artificial intelligence (AI) sector, which is in a pressing need to deliver computing chips to support increasingly complex and diverse cognitive algorithms. This project aims to pioneer such a computing system, including new architectural and design automation tools, for massive AI workloads. The envisioned system will benefit various scenarios, ranging from high-performance computing applications to mobile and edge devices. This project also addresses the skill shortage in the semiconductor area, a crucial aspect for reshoring the semiconductor industry. It involves training students in the areas of heterogeneous system design, AI architectures, and design automation. The investigators plan to improve the knowledge base through new curriculum development, engaging undergraduate students in research through Research Experiences for Undergraduates (REU) supplement, and participating in outreach programs customized for K-12 students. In addition, this project will advocate web-based knowledge dissemination including releasing software codes and novel designs. Several workshops and tutorials promoting chiplet-based co-design have been organized by the investigators and will be continued.Distinguished from current practice of 2.5D/3D heterogeneous integration (HI), this project aims to transform the architecture of chiplet-based design through three unique perspectives: Miniaturization to reduce the chiplet size to the minimum (tiny chiplets) for high composability, guided by AI computing cores; Very-large-scale integration to integrate thousands of tiny chiplets to scale up computing power and diversity for big AI applications, offering unprecedented flexibility and efficiency for AI algorithm and system designers; and Reconfiguration on the package to enable adaptation to varying workloads and address thermal and reliability concerns in 2.5D/3D packaging. These innovations will push the limits of architecture and physical design, addressing challenges related to chiplet definition, interconnection, power and thermal integrity, and workload mapping. The objective is to create a suite of design automation tools, streamlining the complete design process of reconfigurable chiplet-based systems for big AI computing.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着单片芯片达到其技术和实用的极限，芯片集成正在成为不断扩大处理器性能、提高功率效率、以低成本增强IP重用和加快上市时间的主要机制。这种可组合芯片的新概念对人工智能(AI)部门特别有吸引力，该部门迫切需要提供计算芯片，以支持日益复杂和多样化的认知算法。该项目旨在开创这样一种计算系统，包括新的建筑和设计自动化工具，用于大规模人工智能工作负载。设想的系统将使各种场景受益，从高性能计算应用程序到移动和边缘设备。该项目还解决了半导体领域的技能短缺问题，这是半导体行业回流的关键方面。它包括在异类系统设计、人工智能体系结构和设计自动化领域对学生进行培训。研究人员计划通过开发新的课程，通过本科生研究体验(REU)补充材料让本科生参与研究，并参与为K-12学生定制的外展计划，以改善知识基础。此外，该项目将倡导以网络为基础的知识传播，包括发布软件代码和新颖的设计。研究人员已经组织了几个促进基于芯片的协同设计的研讨会和教程，并将继续进行。与当前的2.5D/3D异质集成(HI)实践不同，该项目旨在通过三个独特的角度来改变基于芯片的设计的体系结构：在人工智能计算核心的指导下，将芯片尺寸减小到最小(微小芯片)以实现高可组合性；超大规模集成，以集成数千个微小芯片，以提高大型AI应用的计算能力和多样性，为AI算法和系统设计者提供前所未有的灵活性和效率；并对封装进行重新配置，以适应不同的工作负载，并在2.5D/3D封装中解决散热和可靠性问题。这些创新将突破架构和物理设计的极限，解决与芯片定义、互连、电源和热完整性以及工作负载映射相关的挑战。其目标是创建一套设计自动化工具，简化用于大型人工智能计算的可重新配置的基于芯片的系统的完整设计流程。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。