EAGER: IMPRESS-U: Hardware-Efficient Realization of UA Cryptographic Standards

该项目由NSF、爱沙尼亚研究理事会（ETAG）和美国国家科学院共同支持。该研究将在多边合作伙伴关系中进行，联合卡内基梅隆大学（美国），塔林理工大学（爱沙尼亚）和V.N.Karazin Kharkiv国立大学（乌克兰）。国际研究团队的美国部分由NSF OISE/OD和CISE/CNS共同资助。密码算法使我们能够通过不安全的通信渠道（如互联网）发送秘密信息。这些算法是非常重要的，因为它们使我们的数字生活的几个方面，无论是网上银行，消息服务，移动的电话网络，等等。为了实现这种受保护的通信，并保持相互交谈的各方的隐私，政府机构制定了加密标准。这些标准作为两个设备相互对话的通用语言，同时保护交换消息的内容。例如，在美国，国家标准与技术研究所（NIST）推荐用于民用通信中的加密/解密的高级加密标准（AES）等。AES是在经过长时间的竞争后被选中的，在竞争中考虑了许多候选算法，AES最终成为获胜的算法。今天，有数以百计的软件形式或纯硬件形式的AES实现，即，实现为计算机芯片。在美国之外，还有许多其他标准。在乌克兰，也举办了一场比赛，最终于2015年选出Kalyna和Kupyna作为国家标准。Kalyna和Kupyna的现有软件实现具有与美国同行相当的性能和安全级别。然而，没有已知的硬件架构用于Kalyna或Kupyna的设计。需要具有Kalyna/Kupyna能力的硬件，其显示（i）高性能;（ii）低功率;（iii）防篡改;（iv）小占用空间;以及（v）物理安全性。这是EAGER奖的技术目标，即，为实现分组密码（Kalyna）和散列算法（Kupyna）进行广泛的设计空间和安全空间探索。这个EAGER项目代表了如何在计算机芯片中最好地实现这些算法的研究。研究团队包括来自美国和爱沙尼亚的芯片设计师，以及来自乌克兰的密码学专家。该项目的主要技术成果是一个包含Kalyna和Kupyna算法的几种变体的制造芯片。这个EAGER奖也有传播目标。众所周知，乌克兰无法获得可靠的芯片制造技术。芯片设计知识也很匮乏。我们努力让乌克兰大学在不久的将来教授软件和硬件密码工程。后者是具体的知识，今天，没有充分涵盖的任何大学在该国。为了实现这一目标，在这个项目中执行的芯片设计任务将具有高度的可复制性：设计资源将在公共存储库中公开共享，包括Verilog源文件。最先进的商业芯片设计工具的合成脚本也将共享。最后，整个设计过程将被记录，以展示整个概念的Kalyna/Kupyna芯片，一步一步，从RTL到布局。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

This project is jointly supported by NSF, Estonian Research Council (ETAG), and US National Academy of Sciences. The research will be conducted in multilateral partnership uniting Carnegie Melon University (US), Tallinn University of Technology (Estonia), and V.N.Karazin Kharkiv National University (Ukraine). US part of the international research team is co-funded by NSF OISE/OD and CISE/CNS. Cryptographic algorithms allow us to send secret messages over an otherwise insecure communication channel, such as the internet. These algorithms are extremely important since they enable several aspects of our digital lives, be it online banking, messaging services, mobile phone networks, and many more. To realize such protected communications and maintain the privacy of the parties talking to each other, government agencies set cryptographic standards for adoption. These standards serve as a common language for two devices to talk to one another while keeping the content of the exchange messages protected. For instance, in the US, the National Institute of Standards and Technology (NIST) recommends, among others, the Advanced Encryption Standard (AES) for encryption/decryption in civilian communication. AES was chosen after a long competition where many candidates were considered and AES came out as the winning algorithm. Today, there are hundreds of implementations of AES in software form or in pure hardware form, i.e., implemented as a computer chip. Outside the US, many other standards exist. In Ukraine, a competition was also held which culminated in 2015 with the selection of Kalyna and Kupyna as the national standards. The existing software implementations of Kalyna and Kupyna have performance and security level comparable to their US counterparts. However, there is no known hardware architecture for the design of Kalyna or Kupyna. There is a need for Kalyna/Kupyna-capable hardware that displays (i) high performance; (ii) low power; (iii) tamper resistance; (iv) small footprint; and (v) physical security. This is the technical goal of this EAGER award, i.e., to execute a broad design space and security space exploration for the implementation of a block cipher (Kalyna) and a hash algorithm (Kupyna). This EAGER project represents a study on how to best implement these algorithms in a computer chip. The research team includes chip designers from the US and from Estonia, as well cryptography experts from Ukraine. The main technical outcome of the project is one fabricated chip containing several variants of the Kalyna and Kupyna algorithms. This EAGER award also has dissemination goals. Knowingly, the country of Ukraine does not enjoy access to trusted chip fabrication technology. Chip design knowledge is also scarce. We strive to have Ukrainian universities teaching, in the near future, both software and hardware cryptographic engineering. The latter is specific knowledge that, today, is not adequately covered by any university in the country. In order to achieve this goal, the chip design tasks executed in this project will be highly reproducible: design resources will be openly shared on public repositories, including Verilog source files. Synthesis scripts for state-of-the-art commercial chip design tools will also be shared. Finally, the entire design process will be documented in order to showcase the entire concept of the Kalyna/Kupyna chip, step by step, from RTL to layout. This documented effort will be made openly available to the chip design and cryptographic communities at large.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.