EAGER: IMPRESS-U: Hardware-Efficient Realization of UA Cryptographic Standards

该项目由美国国家科学基金会、爱沙尼亚研究委员会（ETAG）和美国国家科学院联合支持。这项研究将在卡内基梅隆大学（美国）、塔林理工大学（爱沙尼亚）和v.n.卡拉津哈尔科夫国立大学（乌克兰）的多边合作伙伴关系下进行。国际研究团队的美国部分由NSF OISE/OD和CISE/CNS共同资助。加密算法允许我们通过互联网等不安全的通信渠道发送秘密信息。这些算法非常重要，因为它们使我们数字生活的几个方面成为可能，无论是网上银行、短信服务、移动电话网络等等。为了实现这种受保护的通信并维护彼此交谈各方的隐私，政府机构制定了加密标准供采用。这些标准作为两个设备相互通信的通用语言，同时保护交换消息的内容。例如，在美国，国家标准与技术研究所（NIST）推荐使用高级加密标准（AES）来加密/解密民用通信。经过长时间的竞争，许多候选人被考虑，AES最终成为获胜的算法。今天，AES有数百种软件形式或纯硬件形式的实现，即作为计算机芯片实现。在美国之外，还有许多其他的标准。在乌克兰，也举行了一场比赛，最终在2015年选择Kalyna和Kupyna作为国家标准。Kalyna和Kupyna的现有软件实现具有与美国同行相当的性能和安全级别。然而，对于Kalyna或Kupyna的设计，没有已知的硬件架构。需要能够显示(1)高性能的Kalyna/ kupyna硬件；（ii）低功率；（iii）抗篡改；（iv）占地面积小；（五）物理安全。这是本次EAGER奖的技术目标，即为分组密码（Kalyna）和散列算法（Kupyna）的实现执行广泛的设计空间和安全空间探索。这个EAGER项目代表了如何在计算机芯片上最好地实现这些算法的研究。研究团队包括来自美国和爱沙尼亚的芯片设计师，以及来自乌克兰的密码学专家。该项目的主要技术成果是一个包含Kalyna和Kupyna算法的几个变体的制造芯片。这个EAGER奖项也有传播目标。在知情的情况下，乌克兰无法获得可靠的芯片制造技术。芯片设计知识也是稀缺的。我们努力在不久的将来让乌克兰的大学教授软件和硬件加密工程。后者是目前国内任何一所大学都没有充分涵盖的具体知识。为了实现这一目标，在这个项目中执行的芯片设计任务将是高度可重复的：设计资源将在公共存储库上公开共享，包括Verilog源文件。最先进的商业芯片设计工具的合成脚本也将共享。最后，整个设计过程将被记录下来，以展示Kalyna/Kupyna芯片的整个概念，一步一步，从RTL到布局。这一文档化的成果将公开提供给芯片设计和密码学社区。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

This project is jointly supported by NSF, Estonian Research Council (ETAG), and US National Academy of Sciences. The research will be conducted in multilateral partnership uniting Carnegie Melon University (US), Tallinn University of Technology (Estonia), and V.N.Karazin Kharkiv National University (Ukraine). US part of the international research team is co-funded by NSF OISE/OD and CISE/CNS. Cryptographic algorithms allow us to send secret messages over an otherwise insecure communication channel, such as the internet. These algorithms are extremely important since they enable several aspects of our digital lives, be it online banking, messaging services, mobile phone networks, and many more. To realize such protected communications and maintain the privacy of the parties talking to each other, government agencies set cryptographic standards for adoption. These standards serve as a common language for two devices to talk to one another while keeping the content of the exchange messages protected. For instance, in the US, the National Institute of Standards and Technology (NIST) recommends, among others, the Advanced Encryption Standard (AES) for encryption/decryption in civilian communication. AES was chosen after a long competition where many candidates were considered and AES came out as the winning algorithm. Today, there are hundreds of implementations of AES in software form or in pure hardware form, i.e., implemented as a computer chip. Outside the US, many other standards exist. In Ukraine, a competition was also held which culminated in 2015 with the selection of Kalyna and Kupyna as the national standards. The existing software implementations of Kalyna and Kupyna have performance and security level comparable to their US counterparts. However, there is no known hardware architecture for the design of Kalyna or Kupyna. There is a need for Kalyna/Kupyna-capable hardware that displays (i) high performance; (ii) low power; (iii) tamper resistance; (iv) small footprint; and (v) physical security. This is the technical goal of this EAGER award, i.e., to execute a broad design space and security space exploration for the implementation of a block cipher (Kalyna) and a hash algorithm (Kupyna). This EAGER project represents a study on how to best implement these algorithms in a computer chip. The research team includes chip designers from the US and from Estonia, as well cryptography experts from Ukraine. The main technical outcome of the project is one fabricated chip containing several variants of the Kalyna and Kupyna algorithms. This EAGER award also has dissemination goals. Knowingly, the country of Ukraine does not enjoy access to trusted chip fabrication technology. Chip design knowledge is also scarce. We strive to have Ukrainian universities teaching, in the near future, both software and hardware cryptographic engineering. The latter is specific knowledge that, today, is not adequately covered by any university in the country. In order to achieve this goal, the chip design tasks executed in this project will be highly reproducible: design resources will be openly shared on public repositories, including Verilog source files. Synthesis scripts for state-of-the-art commercial chip design tools will also be shared. Finally, the entire design process will be documented in order to showcase the entire concept of the Kalyna/Kupyna chip, step by step, from RTL to layout. This documented effort will be made openly available to the chip design and cryptographic communities at large.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.