A Novel Power Reduction Technique Using Error-resilient Deep Neural Networks for STT-MRAM Based Energy-efficient Brain-inspired Processor Design

点击翻译按钮获取中文摘要

This year, we continued our study on the adaptive quantization algorithm and validated its influence on AI chip performance in terms of algorithms and circuit architecture. A novel adaptive and low-power quantization technique and systematically validates its effectiveness from the algorithm to the hardware module for industrial IoT applications, covering precise navigation for autonomous vehicles and accurate classification utilizing deep neural networks. The proposed quantization method merges an adaptive conversion function from floating-point to fixed-point binaries with an adaptive radix-point determination function, ensuring adequate resolution and minimal error loss of the fixed-point inputs to the edge AI modules. In addition, a hybrid signed convolution module with the architecture of an unsigned divide-and-conquer multiplier is proposed to improve the functional diversity and energy efficiency of artificial intelligence accelerators based on STT-MRAM. The proposed multiplier framework enables different multiplication modes, considerably enhancing the multiplier's versatility for next-generation AI accelerators.