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Development of Delay Performance Driven Logic Circuit Design System

延迟性能驱动逻辑电路设计系统的开发

基本信息

批准号：
05452209
负责人：
KAJITANI Yoji
金额：
$ 4.61万
依托单位：
TOKYO INSTITUTE OF TECHNOLOGY (1995)Japan Advanced Institute of Science and Technology (1993-1994)
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1993
资助国家：
日本
起止时间：
1993 至 1995
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-05452209/
关键词：
VLSI CAD placement logic circuit delay floor plan routing layout synchronous circuit VLSI テクノロジマッピングフロアプランパス遅延矩形限定 FPGA 組み合せアルゴリズム

项目摘要

Two main results obtained in research for automated design system of the delay controlled logic circuits are described in the following.1. High speed logic by controlling clock time :Given a maximum and minimum signal delay of each line segment, a formula for an optimum clock scheduling is developed to provide exact time on which the clock should be provided to each register. A clock distribution with certain allowance to the assigned time is proposed with experiments to verify the idea being effective compared with the conventional methods which aim to reduce both skew of colck time and signal delay.Peripheral technologies : Characterization of logic circuits whose signal delay of each path is observable, Construction of clock distributing trees such that the distance from the source to each leaf point is within certain bound, Delay performance driven clustering of a logic circuit.2. Placement and routing :(1) Expected congestion based layout : A concept of placement based on the expectd wire congestion is proposed with experiments in which a way to determine the evaluation function is offered. The latter idea will initiate a new general methodology in approach to hard problems.(2) Meta-grid placement : Most difficulties in VLSI layout design come from the lack of practical packing technology. We proposed two methods named BSG and SEQ-PAIR.Both are similar in addressing the plane, but each has its advantage in applications. The performance of packing is shown by experiments in a simulated annealing to prove a surprisingly high quality packing of more than five hundred rectangles. Based on this technology, a layout algorithm for analog and printed circuits has been developed taking practical examples.Peripheral technology : Optimum arrangement of cells in gate array disign.

本文介绍了延迟控制逻辑电路自动设计系统研究中的两个主要成果.通过控制时钟时间的高速逻辑：给定每个线段的最大和最小信号延迟，开发最佳时钟调度的公式，以提供时钟应提供给每个寄存器的确切时间。提出了一种对指定时间有一定容差的时钟分配方法，并通过实验验证了该方法的有效性，与传统的同时减小时钟偏差和信号延迟的方法进行了比较。每一路径的信号延迟可观测的逻辑电路的表征，时钟分配树的构造使得从源到每个叶点的距离在一定的范围内，延迟性能驱动的逻辑电路集群.布局与布线：（1）基于期望拥塞的布局：提出了基于期望布线拥塞的布局概念，并给出了评价函数的确定方法。后一种思想将开创一种新的处理难题的一般方法论。(2)元网格布局：VLSI版图设计中的大多数困难来自于缺乏实用的封装技术。本文提出了两种平面寻址方法BSG和SEQ-PAIR，这两种方法在平面寻址上有相似之处，但在应用上各有优势。包装的性能所示的模拟退火实验证明了一个令人惊讶的高品质包装超过500个矩形。在此基础上，结合实例提出了模拟电路和印制电路的布局算法。外围技术：门阵列设计中单元的优化排列。