Combining Topology Synthesis and Physical Design for Wavelength-Routed Optical Networks-on-Chip (WRONoC) — Design Automation Using Physical Layout Templates

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Optical networks-on-chip (ONoC) is an appealing next-generation architecture for on-chip communication in multiprocessor systems-on-chip. Compared to the traditional NoC platforms that use electrical interconnects, ONoCs use optical waveguides to accommodate and transmit optical signals of different wavelengths, and show advantages in high bandwidth, low latency, and distance-independent power consumption. This proposal focuses on a specific family of ONoCs, namely wavelength-routed ONoCs (WRONoCs), which are renowned for supporting all-to-all simultaneous and collision-free data transmission. The state-of-the-art WRONoC design flow is separated into two sequential steps: logic synthesis and physical design, in between of which there is an optimization gap. In the present project, we propose to develop an design automation approach to synthesize and optimize concurrently both the logic topology and the physical layout of a WRONoC design. To reduce the design space to a manageable complexity, we propose to use physical layout templates as additional inputs, which will confine the placement and routing options to a collection of predefined placeholders. To achieve this goal, we will first research the design space of the physical layout templates, and then develop a design automation approach to customize a physical layout template for any given communication graph and layout constraints in an automated manner; integrate the customized template to the optical plane; and synthesize and optimize a complete WRONoC design based on the integrated template. We have tested some manually designed physical layout templates with a prototyped optimization tool and achieved promising results. Thus we are confident that the present project will enable more cost- and energy-efficient WRONoC designs and contribute to the scaling up of this emerging technology.