CRII: SHF: Synthesis of Near-Tree Clock Networks with No Short Circuit Current that Can be Reconfigured into a Tree Topology
CRII: SHF: Synthesis of Near-Tree Clock Networks with No Short Circuit Current that Can be Reconfigured into a Tree Topology
批准号:
1755825
负责人:
Rickard Ewetz
金额:
$17.45万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2018
资助国家:
美国
项目状态:
已结题
起止时间:
2018-07-01 至 2022-06-30
中文摘要
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英文摘要
Many very large scale integration circuits deployed in the Internet of Things and in various high performance applications are required to support the use of high performance and low performance modes in order to minimize power consumption. Such circuits are synchronized by a clock signal that is distributed using a clock network. The clock network is required to reliably deliver the clock signal even while the circuit is under the influence of manufacturing and environmental variations. This research project will result in a clock network synthesis tool that is capable of reliably synchronizing components on circuits that operate in multiple modes. Moreover, a course on computer-aided design and research opportunities will be provided to students at the University of Central Florida. The robustness and power consumption of a clock network is mainly dependent on the topology of the network. Existing clock networks have a topology in the form of a tree, near-tree, or non-tree. In this project, a synthesis tool that is capable of constructing clock networks with a mode reconfigurable topology will be developed. In high performance modes, the required robustness to variations is provided by reconfiguring the clock network into a near-tree topology. In low-performance modes, the power consumption is reduced by reconfiguring the clock network into a tree topology. Moreover, the proposed clock network structure has no short circuit current, regardless of whether the topology is reconfigured to be in the form of a tree or near-tree. No short circuit current is introduced in the proposed structure because there is only a single gate driving each net of interconnects. In particular, the project involves developing an entire-clock-network-at-the-same-time methodology. Techniques of reconfiguring the topology and improving the robustness of delivering both the rising and falling edge of the clock signal will be explored.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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DOI:
10.23919/date48585.2020.9116255
发表时间:
2020-03
期刊:
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
影响因子:
--
作者:
[Baogang Zhang;Necati Uysal;Rickard Ewetz]
通讯作者:
Baogang Zhang;Necati Uysal;Rickard Ewetz
DOI:
10.1145/3453688.3461746
发表时间:
2021-06
期刊:
Proceedings of the 2021 on Great Lakes Symposium on VLSI
影响因子:
--
作者:
[Shravya Channamadhavuni;Sven Thijssen;Sumit Kumar Jha;Rickard Ewetz]
通讯作者:
Shravya Channamadhavuni;Sven Thijssen;Sumit Kumar Jha;Rickard Ewetz
DOI:
10.1109/isvlsi49217.2020.00023
发表时间:
2020-07
期刊:
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
影响因子:
--
作者:
[Baogang Zhang;M. G. Sarwar Murshed;Faraz Hussain;Rickard Ewetz]
通讯作者:
Baogang Zhang;M. G. Sarwar Murshed;Faraz Hussain;Rickard Ewetz
Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current
具有模式可重构拓扑且无短路电流的时钟网络的综合
DOI:
10.1145/3372780.3375559
发表时间:
2020
期刊:
ISPD '20: Proceedings of the 2020 International Symposium on Physical Design
影响因子:
--
作者:
[Uysal, Necati, Cabrera, Juan Ariel, Ewetz, Rickard]
通讯作者:
Ewetz, Rickard
DOI:
10.1109/asp-dac47756.2020.9045101
发表时间:
2019-11
期刊:
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
影响因子:
--
作者:
[Baogang Zhang;Necati Uysal;Deliang Fan;Rickard Ewetz]
通讯作者:
Baogang Zhang;Necati Uysal;Deliang Fan;Rickard Ewetz
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