CRII: SHF: Synthesis of Near-Tree Clock Networks with No Short Circuit Current that Can be Reconfigured into a Tree Topology

在物联网和各种高性能应用中部署的许多非常大规模的集成电路都需要支持高性能和低性能模式的使用，以最大限度地降低功耗。这样的电路由时钟信号同步，该信号通过时钟网络分布。时钟网络被要求即使在电路受到制造和环境变化的影响时也能可靠地传递时钟信号。该研究项目将产生一种时钟网络合成工具，该工具能够在多种模式下运行的电路上可靠地同步组件。此外，将为中佛罗里达大学的学生提供计算机辅助设计和研究机会的课程。时钟网络的鲁棒性和功耗主要取决于网络的拓扑结构。现有的时钟网络具有树、近树或非树形式的拓扑结构。在这个项目中，将开发一个能够构建具有模式可重构拓扑结构的时钟网络的综合工具。在高性能模式下，通过将时钟网络重新配置为近树拓扑结构，可以提供对变化的鲁棒性。在低性能模式下，可以通过将时钟网络重新配置为树型拓扑来降低功耗。此外，无论将拓扑结构重新配置为树状还是近树状，所提出的时钟网络结构都不存在短路电流。该结构中没有引入短路电流，因为只有一个栅极驱动每个互连网。特别是，该项目涉及开发一种同时使用整个时钟网络的方法。将探讨重新配置拓扑和提高传递时钟信号的上升沿和下降沿的鲁棒性的技术。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Many very large scale integration circuits deployed in the Internet of Things and in various high performance applications are required to support the use of high performance and low performance modes in order to minimize power consumption. Such circuits are synchronized by a clock signal that is distributed using a clock network. The clock network is required to reliably deliver the clock signal even while the circuit is under the influence of manufacturing and environmental variations. This research project will result in a clock network synthesis tool that is capable of reliably synchronizing components on circuits that operate in multiple modes. Moreover, a course on computer-aided design and research opportunities will be provided to students at the University of Central Florida. The robustness and power consumption of a clock network is mainly dependent on the topology of the network. Existing clock networks have a topology in the form of a tree, near-tree, or non-tree. In this project, a synthesis tool that is capable of constructing clock networks with a mode reconfigurable topology will be developed. In high performance modes, the required robustness to variations is provided by reconfiguring the clock network into a near-tree topology. In low-performance modes, the power consumption is reduced by reconfiguring the clock network into a tree topology. Moreover, the proposed clock network structure has no short circuit current, regardless of whether the topology is reconfigured to be in the form of a tree or near-tree. No short circuit current is introduced in the proposed structure because there is only a single gate driving each net of interconnects. In particular, the project involves developing an entire-clock-network-at-the-same-time methodology. Techniques of reconfiguring the topology and improving the robustness of delivering both the rising and falling edge of the clock signal will be explored.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.