CRII: SHF: Synthesis of Near-Tree Clock Networks with No Short Circuit Current that Can be Reconfigured into a Tree Topology

CRII：SHF：无短路电流、可重新配置为树形拓扑的近树时钟网络的综合

• 批准号: 1755825
• 负责人: Rickard Ewetz
• 金额: $ 17.45万
• 依托单位: The University of Central Florida Board of Trustees
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-07-01 至 2022-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1755825&HistoricalAwards=false
• 关键词: CRII; SHF; Synthesis; Near; Tree

Many very large scale integration circuits deployed in the Internet of Things and in various high performance applications are required to support the use of high performance and low performance modes in order to minimize power consumption. Such circuits are synchronized by a clock signal that is distributed using a clock network. The clock network is required to reliably deliver the clock signal even while the circuit is under the influence of manufacturing and environmental variations. This research project will result in a clock network synthesis tool that is capable of reliably synchronizing components on circuits that operate in multiple modes. Moreover, a course on computer-aided design and research opportunities will be provided to students at the University of Central Florida. The robustness and power consumption of a clock network is mainly dependent on the topology of the network. Existing clock networks have a topology in the form of a tree, near-tree, or non-tree. In this project, a synthesis tool that is capable of constructing clock networks with a mode reconfigurable topology will be developed. In high performance modes, the required robustness to variations is provided by reconfiguring the clock network into a near-tree topology. In low-performance modes, the power consumption is reduced by reconfiguring the clock network into a tree topology. Moreover, the proposed clock network structure has no short circuit current, regardless of whether the topology is reconfigured to be in the form of a tree or near-tree. No short circuit current is introduced in the proposed structure because there is only a single gate driving each net of interconnects. In particular, the project involves developing an entire-clock-network-at-the-same-time methodology. Techniques of reconfiguring the topology and improving the robustness of delivering both the rising and falling edge of the clock signal will be explored.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

许多部署在物联网和各种高性能应用中的超大规模集成电路都需要支持高性能和低性能模式的使用，以便将功耗降至最低。这样的电路通过使用时钟网络分布的时钟信号来同步。即使在电路受到制造和环境变化的影响时，也需要时钟网络来可靠地传送时钟信号。这项研究项目将产生一种时钟网络综合工具，能够可靠地同步运行在多种模式下的电路上的元件。此外，中佛罗里达大学将向学生提供一门关于计算机辅助设计和研究机会的课程。时钟网络的健壮性和功耗主要取决于网络的拓扑结构。现有时钟网络具有树、近树或非树形式的拓扑。在本项目中，将开发一种能够构建具有模式可重构拓扑的时钟网络的综合工具。在高性能模式下，通过将时钟网络重新配置为近树拓扑来提供对变化所需的稳健性。在低性能模式下，通过将时钟网络重新配置为树形拓扑来降低功耗。此外，所提出的时钟网络结构没有短路电流，无论拓扑是重新配置为树形还是近树形式。在所提出的结构中没有引入短路电流，因为只有一个栅极驱动每个互连网络。特别是，该项目涉及开发一种同时使用全时钟网络的方法。将探索重新配置拓扑结构和提高提供时钟信号上升沿和下降沿的稳健性的技术。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays

• DOI: 10.23919/date48585.2020.9116255
• 发表时间: 2020-03
• 期刊: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
• 作者: Baogang Zhang;Necati Uysal;Rickard Ewetz

Accelerating AI Applications using Analog In-Memory Computing: Challenges and Opportunities

• DOI: 10.1145/3453688.3461746
• 发表时间: 2021-06
• 期刊: Proceedings of the 2021 on Great Lakes Symposium on VLSI
• 作者: Shravya Channamadhavuni;Sven Thijssen;Sumit Kumar Jha;Rickard Ewetz

Fast Resilient-Aware Data Layout Organization for Resistive Computing Systems

• DOI: 10.1109/isvlsi49217.2020.00023
• 发表时间: 2020-07
• 期刊: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
• 作者: Baogang Zhang;M. G. Sarwar Murshed;Faraz Hussain;Rickard Ewetz

Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current

具有模式可重构拓扑且无短路电流的时钟网络的综合

• DOI: 10.1145/3372780.3375559
• 发表时间: 2020
• 期刊: ISPD '20: Proceedings of the 2020 International Symposium on Physical Design
• 作者: Uysal, Necati;Cabrera, Juan Ariel;Ewetz, Rickard
• 通讯作者: Ewetz, Rickard

Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors

• DOI: 10.1109/asp-dac47756.2020.9045101
• 发表时间: 2019-11
• 期刊: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
• 作者: Baogang Zhang;Necati Uysal;Deliang Fan;Rickard Ewetz